s32v234 datesheet(S32V234RM.pdf)

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ContentsSection number Title PageChapter 1About This Manual1.1 Audience....................................................................................................................................................................... 1211.2 Organization..................................................................................................................................................................1211.2.1 Attachments................................................................................................................................................. 1211.3 Module descriptions......................................................................................................................................................1211.3.1 Example: chip-specific information that clarifies content in the same chapter........................................... 1221.3.2 Example: chip-specific information that refers to a different chapter......................................................... 1231.4 Register descriptions.....................................................................................................................................................1241.5 Conventions.................................................................................................................................................................. 1251.5.1 Notes, Cautions, and Warnings....................................................................................................................1251.5.2 Numbering systems......................................................................................................................................1251.5.3 Typographic notation................................................................................................................................... 1261.5.4 Special terms................................................................................................................................................ 126Chapter 2Introduction2.1 Introduction...................................................................................................................................................................1292.1.1 Target applications.......................................................................................................................................1302.1.2 Block diagram.............................................................................................................................................. 1302.1.3 Device Configuration...................................................................................................................................1302.1.4 Feature Set....................................................................................................................................................134Chapter 3Embedded Memory Overview3.1 Memory structure..........................................................................................................................................................1373.2 Attached peripheral memory map.................................................................................................................................1393.3 VSEQ memory map......................................................................................................................................................1393.4 Validation of error correction/detection........................................................................................................................139Chapter 4S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 3Section number Title PageMemory Map4.1 Peripheral Memory Map...............................................................................................................................................1414.2 Private Peripheral Bus (PPB) memory map..................................................................................................................1414.3 Interrupt Map................................................................................................................................................................ 142Chapter 5Signal Description5.1 Signal Description.........................................................................................................................................................1455.1.1 Miscellaneous Pins.......................................................................................................................................1455.1.2 I/O Behavior During Reset.......................................................................................................................... 1465.2 RESET pin behaviour during selftest........................................................................................................................... 146Chapter 6ARM Modules6.1 Glossary........................................................................................................................................................................ 1476.2 Platform components.................................................................................................................................................... 1476.3 Cortex-A53 cluster complex.........................................................................................................................................1496.3.1 ARM Cortex-A53 MPCore..........................................................................................................................1506.3.2 ARM Generic Interrupt Controller (GIC-400).............................................................................................1526.3.3 ARM CoreLink CCI-400 Cache Coherent Interconnect..............................................................................1546.4 Cortex-M4 processor.................................................................................................................................................... 1566.5 CoreLink Network Interconnect NIC-301....................................................................................................................1566.6 Extended Resource Domain Controller (XRDC)......................................................................................................... 1576.7 Operational Details....................................................................................................................................................... 1576.7.1 Cluster reset..................................................................................................................................................1576.7.2 Cluster clock gating..................................................................................................................................... 157Chapter 7Enhanced Direct Memory Access (eDMA)7.1 Chip specific eDMA information................................................................................................................................. 1597.2 Introduction...................................................................................................................................................................1597.2.1 eDMA system block diagram...................................................................................................................... 1597.2.2 Block parts................................................................................................................................................... 160S32V234 Reference Manual, Rev. 5, 11/20194 NXP SemiconductorsSection number Title Page7.2.3 Features........................................................................................................................................................ 1617.3 Modes of operation....................................................................................................................................................... 1627.4 Memory map/register definition................................................................................................................................... 1637.4.1 TCD memory............................................................................................................................................... 1637.4.2 TCD initialization........................................................................................................................................ 1637.4.3 TCD structure...............................................................................................................................................1637.4.4 Reserved memory and bit fields...................................................................................................................1647.4.5 Control Register (DMA_CR).......................................................................................................................1867.4.6 Error Status Register (DMA_ES)................................................................................................................ 1897.4.7 Enable Request Register (DMA_ERQ)....................................................................................................... 1927.4.8 Enable Error Interrupt Register (DMA_EEI)...............................................................................................1957.4.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 1997.4.10 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 2007.4.11 Clear Enable Request Register (DMA_CERQ)........................................................................................... 2007.4.12 Set Enable Request Register (DMA_SERQ)............................................................................................... 2017.4.13 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................ 2027.4.14 Set START Bit Register (DMA_SSRT)...................................................................................................... 2037.4.15 Clear Error Register (DMA_CERR)............................................................................................................2047.4.16 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 2057.4.17 Interrupt Request Register (DMA_INT)......................................................................................................2067.4.18 Error Register (DMA_ERR)........................................................................................................................ 2097.4.19 Hardware Request Status Register (DMA_HRS)........................................................................................ 2137.4.20 General-Purpose Output Register (DMA_GPORn).....................................................................................2197.4.21 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 2207.4.22 Channel n Master ID Register (DMA_DCHMIDn).................................................................................... 2217.4.23 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................2227.4.24 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................2227.4.25 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................2227.4.26 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 223S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 5Section number Title Page7.4.27 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)(DMA_TCDn_NBYTES_MLOFFNO)....................................................................................................... 2247.4.28 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 2257.4.29 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................2267.4.30 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................2277.4.31 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................2277.4.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)(DMA_TCDn_CITER_ELINKYES)...........................................................................................................2287.4.33 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 2297.4.34 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 2307.4.35 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 2307.4.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)(DMA_TCDn_BITER_ELINKYES)...........................................................................................................2337.4.37 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 2347.5 Functional description...................................................................................................................................................2347.5.1 eDMA basic data flow................................................................................................................................. 2357.5.2 Fault reporting and handling........................................................................................................................ 2377.5.3 Channel preemption..................................................................................................................................... 2407.6 Initialization/application information........................................................................................................................... 2407.6.1 eDMA initialization..................................................................................................................................... 2407.6.2 Programming errors..................................................................................................................................... 2437.6.3 Arbitration mode considerations..................................................................................................................2447.6.4 Performing DMA transfers.......................................................................................................................... 2457.6.5 Monitoring transfer descriptor status........................................................................................................... 2497.6.6 Channel Linking...........................................................................................................................................2517.6.7 Dynamic programming................................................................................................................................ 2527.6.8 Suspend/resume a DMA channel with active hardware service requests....................................................255S32V234 Reference Manual, Rev. 5, 11/20196 NXP SemiconductorsSection number Title PageChapter 8Direct Memory Access Multiplexer (DMAMUX)8.1 Chip specific DMAMUX information..........................................................................................................................2578.1.1 DMAMUX instantiation information.......................................................................................................... 2578.1.2 DMA Request Source Slot Mapping........................................................................................................... 2578.1.3 DMAMUX Trigger Channel Assignment....................................................................................................2598.2 Introduction...................................................................................................................................................................2608.2.1 Overview......................................................................................................................................................2608.2.2 Features........................................................................................................................................................ 2618.2.3 Modes of operation...................................................................................................................................... 2618.3 External signal description............................................................................................................................................2618.4 Memory map/register definition................................................................................................................................... 2628.4.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 2628.5 Functional description...................................................................................................................................................2638.5.1 DMA channels with periodic triggering capability......................................................................................2638.5.2 DMA channels with no triggering capability...............................................................................................2668.5.3 Always-enabled DMA sources.................................................................................................................... 2668.6 Initialization/application information........................................................................................................................... 2668.6.1 Reset.............................................................................................................................................................2668.6.2 Enabling and configuring sources................................................................................................................267Chapter 9NIC3019.1 CoreLink Network Interconnect NIC-301....................................................................................................................2719.2 Overview.......................................................................................................................................................................2719.3 Features.........................................................................................................................................................................2719.4 NIC301 Physical Structure and Programming Model.................................................................................................. 2729.4.1 NIC301 Physical Structure...........................................................................................................................2729.4.2 NIC301 Programming Model...................................................................................................................... 2759.4.3 NIC-301 register summary...........................................................................................................................276S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 7Section number Title Page9.4.4 NIC301 Special Software Setup Requirements........................................................................................... 3149.4.5 NIC301 Bus Arbitration...............................................................................................................................314Chapter 10Crossbar Switch (AXBS)10.1 Chip specific AXBS information..................................................................................................................................31710.1.1 AXBS configuration.................................................................................................................................... 31710.1.2 XBAR master assignments.......................................................................................................................... 31910.1.3 XBAR slave assignments.............................................................................................................................31910.1.4 AXBS Connectivity .................................................................................................................................... 32010.1.5 Unimplemented PRSn and CRSn registers..................................................................................................32010.2 Introduction...................................................................................................................................................................32010.2.1 Features........................................................................................................................................................ 32110.3 Memory Map / Register Definition...............................................................................................................................32110.3.1 Priority Registers Slave (AXBS_PRSn)...................................................................................................... 32310.3.2 Control Register (AXBS_CRSn)................................................................................................................. 32610.3.3 Master General Purpose Control Register (AXBS_MGPCRn)................................................................... 32810.4 Functional Description..................................................................................................................................................32910.4.1 General operation.........................................................................................................................................32910.4.2 Register coherency.......................................................................................................................................330Chapter 11Extended Resource Domain Controller (XRDC)11.1 Chip specific XRDC information................................................................................................................................. 33111.1.1 XRDC memory map.................................................................................................................................... 33111.1.2 Register configuration..................................................................................................................................35811.2 Introduction...................................................................................................................................................................36011.2.1 Features........................................................................................................................................................ 36111.2.2 Block diagram.............................................................................................................................................. 36211.2.3 Modes of operation...................................................................................................................................... 36311.3 External signal description............................................................................................................................................364S32V234 Reference Manual, Rev. 5, 11/20198 NXP SemiconductorsSection number Title Page11.4 Register definition.........................................................................................................................................................36411.4.1 Control Register (XRDC_CR)..................................................................................................................... 36511.4.2 Hardware Configuration Register 0 (XRDC_HWCFG0)............................................................................36711.4.3 Hardware Configuration Register 1 (XRDC_HWCFG1)............................................................................36811.4.4 Hardware Configuration Register 2 (XRDC_HWCFG2)............................................................................36811.4.5 Master Domain Assignment Configuration Register (XRDC_MDACFGn)...............................................37311.4.6 Memory Region Configuration Register (XRDC_MRCFGn).....................................................................37411.4.7 Domain Error Location Register (XRDC_DERRLOCn)............................................................................ 37511.4.8 Domain Error Word0 Register (XRDC_DERR_W0_n)..............................................................................37611.4.9 Domain Error Word1 Register (XRDC_DERR_W1_n)..............................................................................37711.4.10 Domain Error Word2 Register (XRDC_DERR_W2_n)..............................................................................37811.4.11 Domain Error Word3 Register (XRDC_DERR_W3_n)..............................................................................37911.4.12 Process Identifier (XRDC_PIDn)................................................................................................................ 37911.4.13 Master Domain Assignment Wm,n (DFMT=0) (XRDC_MDA_Wm_n)....................................................38211.4.14 Master Domain Assignment Wm,n (DFMT=1) (XRDC_MDA_Wm_n)....................................................38511.4.15 Peripheral Domain Access Control W0 (XRDC_PDAC_W0_n)................................................................38711.4.16 Peripheral Domain Access Control W1 (XRDC_PDAC_W1_n)................................................................38911.4.17 Memory Region Descriptor W0 (XRDC_MRGD_W0_n).......................................................................... 38911.4.18 Memory Region Descriptor W1 (XRDC_MRGD_W1_n).......................................................................... 39111.4.19 Memory Region Descriptor W2 (XRDC_MRGD_W2_n).......................................................................... 39111.4.20 Memory Region Descriptor W3 (XRDC_MRGD_W3_n).......................................................................... 39311.4.21 S32V234 specific MRC instance for SRAM controller memory protection............................................... 39311.5 Functional description...................................................................................................................................................39811.5.1 Manager (XRDC_MGR)..............................................................................................................................39811.5.2 Master Domain Assignment Controller (XRDC_MDAC).......................................................................... 39911.5.3 DxACP evaluation....................................................................................................................................... 40011.5.4 Hardware semaphores and dynamic access rights....................................................................................... 40111.5.5 Memory Region Controller (XRDC_MRC)................................................................................................ 40211.5.6 Peripheral Access Controller (XRDC_PAC)...............................................................................................406S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 9Section number Title Page11.6 Initialization information.............................................................................................................................................. 40811.7 Application information................................................................................................................................................40911.7.1 Master domain assignments......................................................................................................................... 40911.7.2 Cache coherency interconnect (CCI)........................................................................................................... 41011.7.3 Memory region descriptor management...................................................................................................... 41211.7.4 Domain error capture management..............................................................................................................413Chapter 12Semaphores2 (SEMA42)12.1 Introduction...................................................................................................................................................................41512.1.1 Features........................................................................................................................................................ 41512.2 Memory map/register definition................................................................................................................................... 41712.2.1 Gate Register (SEMA42_GATEn).............................................................................................................. 41812.2.2 Reset Gate Write (SEMA42_RSTGT_W)...................................................................................................41912.2.3 Reset Gate Read (SEMA42_RSTGT_R).....................................................................................................42112.3 Functional description...................................................................................................................................................421Chapter 13Local Memory (LMEM) Controller13.1 Introduction...................................................................................................................................................................42513.1.1 Block diagram.............................................................................................................................................. 42513.1.2 Cache features.............................................................................................................................................. 42713.2 Memory map/register definition................................................................................................................................... 42813.2.1 Processor Code Cache Control Register (LMEM_PCCCR)........................................................................42913.2.2 Processor Code Cache Line Control Register (LMEM_PCCLCR).............................................................43013.2.3 Processor Code Cache Search Address Register (LMEM_PCCSAR)........................................................ 43313.2.4 Processor Code Cache Read/Write Value Register (LMEM_PCCCVR)....................................................43413.2.5 Processor System Cache Control Register (LMEM_PSCCR).....................................................................43413.2.6 Processor System Cache Line Control Register (LMEM_PSCLCR)..........................................................43613.2.7 Processor System Cache Search Address Register (LMEM_PSCSAR)..................................................... 43813.2.8 Processor System Cache Read/Write Value Register (LMEM_PSCCVR)................................................. 439S32V234 Reference Manual, Rev. 5, 11/201910 NXP SemiconductorsSection number Title Page13.3 Functional description...................................................................................................................................................43913.3.1 LMEM function........................................................................................................................................... 43913.3.2 SRAM function............................................................................................................................................ 44013.3.3 Cache function............................................................................................................................................. 44213.3.4 Cache control............................................................................................................................................... 442Chapter 14Error Reporting Module (ERM)14.1 Chip-specific ERM information................................................................................................................................... 44714.1.1 ERM memory channels................................................................................................................................44714.1.2 Memory error event sources and captured information............................................................................... 44714.2 Introduction...................................................................................................................................................................44814.2.1 Overview......................................................................................................................................................44814.2.2 Features........................................................................................................................................................ 44814.3 Memory map and register definition.............................................................................................................................44914.3.1 ERM Configuration Register (ERM_CR)....................................................................................................45014.3.2 ERM Status Register (ERM_SR).................................................................................................................45314.3.3 ERM Memory n Error Address Register (ERM_EARn)............................................................................. 45614.3.4 ERM Memory n Syndrome Register (ERM_SYNn)................................................................................... 45714.4 Functional description...................................................................................................................................................45714.4.1 Single-bit correction events......................................................................................................................... 45714.4.2 Non-correctable error events........................................................................................................................45814.5 Initialization.................................................................................................................................................................. 459Chapter 15Error Injection Module (EIM)15.1 Chip-specific EIM information.....................................................................................................................................46115.1.1 EIM channels............................................................................................................................................... 46115.1.2 EIM channel assignments............................................................................................................................ 46115.1.3 EIM_EICHDn_WORD register bit mapping...............................................................................................46215.2 Introduction...................................................................................................................................................................464S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 11Section number Title Page15.2.1 Overview......................................................................................................................................................46415.2.2 Features........................................................................................................................................................ 46515.3 Memory map and register definition.............................................................................................................................46615.3.1 Error Injection Module Configuration Register (EIM_EIMCR)................................................................. 46915.3.2 Error Injection Channel Enable register (EIM_EICHEN)...........................................................................46915.3.3 Error Injection Channel Descriptor, Word0 (EIM_EICHDn_WORD0)..................................................... 47315.3.4 Error Injection Channel Descriptor, Word1 (EIM_EICHDn_WORD1)..................................................... 47415.3.5 Error Injection Channel Descriptor, Word2 (EIM_EICHDn_WORD2)..................................................... 47515.4 Functional description...................................................................................................................................................47515.4.1 Error injection scenarios.............................................................................................................................. 476Chapter 16Interrupt Monitor (INTM)16.1 Introduction...................................................................................................................................................................47716.2 Block diagram...............................................................................................................................................................47816.3 Features.........................................................................................................................................................................47816.4 INTM Register Descriptions.........................................................................................................................................47916.4.1 INTM Memory Map.................................................................................................................................... 47916.4.2 Monitor Mode (INTM_MM)....................................................................................................................... 47916.4.3 Interrupt Acknowledge (INTM_IACK).......................................................................................................48016.4.4 Interrupt Request Select a (INTM_IRQSELa).............................................................................................48116.4.5 Latency a (INTM_LATENCYa)..................................................................................................................48216.4.6 Timer a (INTM_TIMERa)........................................................................................................................... 48316.4.7 Status a (INTM_STATUSa)........................................................................................................................ 48516.5 Functional description...................................................................................................................................................486Chapter 17Miscellaneous Control Module (MCM)17.1 Introduction...................................................................................................................................................................48917.1.1 Features........................................................................................................................................................ 48917.2 Memory map/register descriptions............................................................................................................................... 489S32V234 Reference Manual, Rev. 5, 11/201912 NXP SemiconductorsSection number Title Page17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................49017.2.2 Control Register (MCM_CR)...................................................................................................................... 49117.2.3 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 49217.2.4 Fault address register (MCM_FADR)......................................................................................................... 49517.2.5 Fault attributes register (MCM_FATR).......................................................................................................49617.2.6 Fault data register (MCM_FDR)..................................................................................................................497Chapter 18Miscellaneous System Control Module (MSCM)18.1 Introduction...................................................................................................................................................................49918.2 Memory map and register definition.............................................................................................................................49918.2.1 CPU configuration registers.........................................................................................................................49918.2.2 On-chip memory (OCMEM) configuration registers.................................................................................. 50018.2.3 Interrupt router configuration registers........................................................................................................ 50018.2.4 Burst optimization control register.............................................................................................................. 50118.2.5 Processor x Type Register (MSCM_CPXTYPE)........................................................................................ 51118.2.6 Processor x Number Register (MSCM_CPXNUM)....................................................................................51218.2.7 Processor x Master Number Register (MSCM_CPXMASTER).................................................................51318.2.8 Processor x Count Register (MSCM_CPXCOUNT)...................................................................................51318.2.9 Processor x Configuration 0 Register (MSCM_CPXCFG0)....................................................................... 51418.2.10 Processor x Configuration 1 Register (MSCM_CPXCFG1)....................................................................... 51618.2.11 Processor x Configuration 2 Register (MSCM_CPXCFG2)....................................................................... 51718.2.12 Processor x Configuration 3 Register (MSCM_CPXCFG3)....................................................................... 51918.2.13 Processor 0 Type Register (MSCM_CP0TYPE)......................................................................................... 52018.2.14 Processor 0 Number Register (MSCM_CP0NUM).....................................................................................52118.2.15 Processor 0 Master Number Register (MSCM_CP0MASTER)..................................................................52218.2.16 Processor 0 Count Register (MSCM_CP0COUNT)....................................................................................52318.2.17 Processor 0 Configuration 0 Register (MSCM_CP0CFG0)........................................................................ 52418.2.18 Processor 0 Configuration 1 Register (MSCM_CP0CFG1)........................................................................ 52518.2.19 Processor 0 Configuration 2 Register (MSCM_CP0CFG2)........................................................................ 526S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 13Section number Title Page18.2.20 Processor 0 Configuration 3 Register (MSCM_CP0CFG3)........................................................................ 52818.2.21 Processor 1 Type Register (MSCM_CP1TYPE)......................................................................................... 53018.2.22 Processor 1 Number Register (MSCM_CP1NUM).....................................................................................53018.2.23 Processor 1 Master Number Register (MSCM_CP1MASTER)..................................................................53118.2.24 Processor 1 Count Register (MSCM_CP1COUNT)....................................................................................53218.2.25 Processor 1 Configuration 0 Register (MSCM_CP1CFG0)........................................................................ 53318.2.26 Processor 1 Configuration 1 Register (MSCM_CP1CFG1)........................................................................ 53418.2.27 Processor 1 Configuration 2 Register (MSCM_CP1CFG2)........................................................................ 53518.2.28 Processor 1 Configuration 3 Register (MSCM_CP1CFG3)........................................................................ 53718.2.29 On-Chip Memory Descriptor Register (MSCM_OCMDRn)...................................................................... 53918.2.30 Generic Tightly Coupled Memory Descriptor Register (MSCM_TCMDR0).............................................54418.2.31 Core Parity Checking Enable Register 0 (MSCM_CPCE0)........................................................................54618.2.32 Interrupt Router CP0 Interrupt Register (MSCM_IRCP0IR)...................................................................... 54718.2.33 Interrupt Router CP1 Interrupt Register (MSCM_IRCP1IR)...................................................................... 54918.2.34 Interrupt Router CPU Generate Interrupt Register (MSCM_IRCPGIR).....................................................55018.2.35 Interrupt Router Shared Peripheral Routing Control Register (MSCM_IRSPRCn)................................... 55118.2.36 Interconnect Parity Checking Global Enable Register (MSCM_IPCGE)................................................... 55218.2.37 Interconnect Parity Checking Enable Register 0 (MSCM_IPCE0)............................................................. 55318.2.38 Interconnect Parity Checking Enable Register 1 (MSCM_IPCE1)............................................................. 55718.2.39 Interconnect Parity Checking Enable Register 2 (MSCM_IPCE2)............................................................. 56118.2.40 Interconnect Parity Checking Enable Register 3 (MSCM_IPCE3)............................................................. 56418.2.41 Interconnect Parity Checking Global Injection Enable Register (MSCM_IPCGIE)...................................56718.2.42 Interconnect Parity Checking Injection Enable Register 0 (MSCM_IPCIE0)............................................ 56818.2.43 Interconnect Parity Checking Injection Enable Register 1 (MSCM_IPCIE1)............................................ 57318.2.44 Interconnect Parity Checking Injection Enable Register 2 (MSCM_IPCIE2)............................................ 57718.2.45 Interconnect Parity Checking Injection Enable Register 3 (MSCM_IPCIE3)............................................ 58018.3 Chip configuration and boot......................................................................................................................................... 58318.4 Interrupt steering and semaphores................................................................................................................................ 58418.4.1 Interrupt handling overview.........................................................................................................................584S32V234 Reference Manual, Rev. 5, 11/201914 NXP SemiconductorsSection number Title Page18.4.2 MSCM interrupt router functional description............................................................................................ 585Chapter 19Crossbar Integrity Checker (XBIC)19.1 Overview.......................................................................................................................................................................58919.2 Features.........................................................................................................................................................................58919.3 Block diagram...............................................................................................................................................................58919.4 External signal description............................................................................................................................................59019.5 Memory map and register definition.............................................................................................................................59019.5.1 XBIC Module Control Register (XBIC_MCR)........................................................................................... 59119.5.2 XBIC Error Injection Register (XBIC_EIR)............................................................................................... 59319.5.3 XBIC Error Status Register (XBIC_ESR)................................................................................................... 59319.5.4 XBIC Error Address Register (XBIC_EAR)............................................................................................... 59619.6 Functional description...................................................................................................................................................597Chapter 20System Integration Unit Lite2 (SIUL2)20.1 Introduction...................................................................................................................................................................59920.1.1 Overview......................................................................................................................................................59920.1.2 Features........................................................................................................................................................ 60120.2 Memory map and register description.......................................................................................................................... 60220.2.1 SIUL2 MCU ID Register #1 (SIUL2_MIDR1)........................................................................................... 64720.2.2 SIUL2 MCU ID Register #2 (SIUL2_MIDR2)........................................................................................... 64820.2.3 SIUL2 DMA/Interrupt Status Flag Register0 (SIUL2_DISR0).................................................................. 64920.2.4 SIUL2 DMA/Interrupt Request Enable Register0 (SIUL2_DIRER0)........................................................ 65420.2.5 SIUL2 DMA/Interrupt Request Select Register0 (SIUL2_DIRSR0).......................................................... 65720.2.6 SIUL2 Interrupt Rising-Edge Event Enable Register 0 (SIUL2_IREER0).................................................66120.2.7 SIUL2 Interrupt Falling-Edge Event Enable Register 0 (SIUL2_IFEER0)................................................ 66420.2.8 SIUL2 Interrupt Filter Enable Register 0 (SIUL2_IFER0)......................................................................... 66820.2.9 SIUL2 Interrupt Filter Maximum Counter Register (SIUL2_IFMCRn)..................................................... 67120.2.10 SIUL2 Interrupt Filter Clock Prescaler Register (SIUL2_IFCPR)..............................................................672S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 15Section number Title Page20.2.11 SIUL2 Multiplexed Signal Configuration (SIUL2_MSCRn)......................................................................67320.2.12 SIUL2 Input Multiplexed Signal Configuration Register (SIUL2_IMCRn)............................................... 67920.2.13 SIUL2 GPIO Pad Data Output Register (SIUL2_GPDOn)......................................................................... 68020.2.14 SIUL2 GPIO Pad Data Input Register (SIUL2_GPDIn)............................................................................. 68220.2.15 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO1)...............................................................68420.2.16 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO0)...............................................................68520.2.17 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO3)...............................................................68620.2.18 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO2)...............................................................68720.2.19 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO5)...............................................................68820.2.20 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO4)...............................................................68920.2.21 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO7)...............................................................69020.2.22 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO6)...............................................................69120.2.23 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO9)...............................................................69220.2.24 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO8)...............................................................69320.2.25 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO10).............................................................69420.2.26 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI1)...................................................................69520.2.27 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI0)...................................................................69520.2.28 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI3)...................................................................69620.2.29 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI2)...................................................................69720.2.30 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI5)...................................................................69820.2.31 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI4)...................................................................69820.2.32 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI7)...................................................................69920.2.33 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI6)...................................................................70020.2.34 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI9)...................................................................70120.2.35 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI8)...................................................................70120.2.36 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI10).................................................................70220.2.37 SIUL2 Masked Parallel GPIO Pad Data Out Register (SIUL2_MPGPDOn)............................................. 70320.3 Functional description...................................................................................................................................................70420.3.1 General......................................................................................................................................................... 704S32V234 Reference Manual, Rev. 5, 11/201916 NXP SemiconductorsSection number Title Page20.3.2 Pad Control.................................................................................................................................................. 70420.3.3 General Purpose Input and Output pads...................................................................................................... 70520.3.4 External interrupts/DMA requests (EIRQ Pins).......................................................................................... 706Chapter 21Wakeup Unit (WKPU)21.1 Chip specific WKPU information.................................................................................................................................71121.1.1 WKPU configuration................................................................................................................................... 71121.2 Introduction...................................................................................................................................................................71221.3 Features.........................................................................................................................................................................71221.4 WKPU memory map and register definition................................................................................................................ 71321.4.1 NMI Status Flag Register (WKPU_NSR)................................................................................................... 71321.4.2 NMI Configuration Register (WKPU_NCR).............................................................................................. 71521.5 Functional description...................................................................................................................................................71721.5.1 Non-maskable interrupts.............................................................................................................................. 71721.6 Initialization Information..............................................................................................................................................71921.6.1 Glitch Filter and Pad Configuration.............................................................................................................71921.6.2 Non-Maskable Interrupts............................................................................................................................. 719Chapter 22Clocking22.1 Introduction...................................................................................................................................................................72122.2 Clock Generation.......................................................................................................................................................... 72422.2.1 MC_CGM Registers.................................................................................................................................... 72822.2.2 System clock frequency limitations............................................................................................................. 73022.3 Clock sources................................................................................................................................................................73222.3.1 PLLs............................................................................................................................................................. 73222.3.2 FXOSC.........................................................................................................................................................73822.3.3 FIRC.............................................................................................................................................................73922.3.4 Clock sources — memory map....................................................................................................................73922.4 Default clock configuration.......................................................................................................................................... 740S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 17Section number Title Page22.5 Clock Gating................................................................................................................................................................. 74022.6 Clock Monitoring..........................................................................................................................................................74322.6.1 Introduction..................................................................................................................................................74322.6.2 CMU configuration...................................................................................................................................... 74322.6.3 Clock input sources......................................................................................................................................74522.6.4 CMU Memory Map..................................................................................................................................... 74622.6.5 CMU registers and field availability ...........................................................................................................74622.6.6 CMU register write protection..................................................................................................................... 74722.7 Peripheral clocking ...................................................................................................................................................... 74722.7.1 Safety modules.............................................................................................................................................74922.7.2 Memory system............................................................................................................................................75122.7.3 CPU timer modules......................................................................................................................................75422.7.4 Communication interface modules.............................................................................................................. 75622.7.5 Generic modules.......................................................................................................................................... 76522.7.6 Video Processing Modules...........................................................................................................................76622.7.7 Analog Modules...........................................................................................................................................77322.7.8 Boot modules............................................................................................................................................... 77522.7.9 Compute and bus modules........................................................................................................................... 77522.8 LBIST Clocking............................................................................................................................................................779Chapter 23Clock Generation Module (MC_CGM)23.1 Introduction...................................................................................................................................................................78123.1.1 Overview......................................................................................................................................................78123.1.2 Features........................................................................................................................................................ 78223.2 Memory map and register definition.............................................................................................................................78323.3 MC_CGM_0 registers...................................................................................................................................................78323.3.1 PCS Switch Duration Register (MC_CGM_0_PCS_SDUR)...................................................................... 78623.3.2 PCS Divider Change Register 2 (MC_CGM_0_PCS_DIVC2)...................................................................78623.3.3 PCS Divider End Register 2 (MC_CGM_0_PCS_DIVE2).........................................................................787S32V234 Reference Manual, Rev. 5, 11/201918 NXP SemiconductorsSection number Title Page23.3.4 PCS Divider Start Register 2 (MC_CGM_0_PCS_DIVS2)........................................................................ 78823.3.5 Divider Update Type Register (MC_CGM_0_DIV_UPD_TYPE)............................................................. 78823.3.6 Divider Update Trigger Register (MC_CGM_0_DIV_UPD_TRIG).......................................................... 79023.3.7 Divider Update Status Register (MC_CGM_0_DIV_UPD_STAT)............................................................79023.3.8 System Clock Select Status Register (MC_CGM_0_SC_SS)..................................................................... 79223.3.9 System Clock Divider 0 Configuration Register (MC_CGM_0_SC_DC0)................................................79323.3.10 System Clock Divider 1 Configuration Register (MC_CGM_0_SC_DC1)................................................79423.3.11 System Clock Divider 2 Configuration Register (MC_CGM_0_SC_DC2)................................................79523.3.12 Auxiliary Clock 0 Select Control Register (MC_CGM_0_AC0_SC)......................................................... 79623.3.13 Auxiliary Clock 0 Select Status Register (MC_CGM_0_AC0_SS)............................................................79723.3.14 Auxiliary Clock 0 Divider 0 Configuration Register (MC_CGM_0_AC0_DC0).......................................79823.3.15 Auxiliary Clock 1 Select Control Register (MC_CGM_0_AC1_SC)......................................................... 79823.3.16 Auxiliary Clock 1 Select Status Register (MC_CGM_0_AC1_SS)............................................................79923.3.17 Auxiliary Clock 1 Divider 0 Configuration Register (MC_CGM_0_AC1_DC0).......................................80023.3.18 Auxiliary Clock 2 Select Control Register (MC_CGM_0_AC2_SC)......................................................... 80123.3.19 Auxiliary Clock 2 Select Status Register (MC_CGM_0_AC2_SS)............................................................80223.3.20 Auxiliary Clock 2 Divider 0 Configuration Register (MC_CGM_0_AC2_DC0).......................................80323.3.21 Auxiliary Clock 3 Select Control Register (MC_CGM_0_AC3_SC)......................................................... 80423.3.22 Auxiliary Clock 3 Select Status Register (MC_CGM_0_AC3_SS)............................................................80423.3.23 Auxiliary Clock 3 Divider 0 Configuration Register (MC_CGM_0_AC3_DC0).......................................80523.3.24 Auxiliary Clock 4 Select Control Register (MC_CGM_0_AC4_SC)......................................................... 80623.3.25 Auxiliary Clock 4 Select Status Register (MC_CGM_0_AC4_SS)............................................................80723.3.26 Auxiliary Clock 4 Divider 0 Configuration Register (MC_CGM_0_AC4_DC0).......................................80823.3.27 Auxiliary Clock 5 Select Control Register (MC_CGM_0_AC5_SC)......................................................... 80923.3.28 Auxiliary Clock 5 Select Status Register (MC_CGM_0_AC5_SS)............................................................81023.3.29 Auxiliary Clock 5 Divider 0 Configuration Register (MC_CGM_0_AC5_DC0).......................................81123.3.30 Auxiliary Clock 5 Divider 1 Configuration Register (MC_CGM_0_AC5_DC1).......................................81123.3.31 Auxiliary Clock 6 Select Control Register (MC_CGM_0_AC6_SC)......................................................... 81223.3.32 Auxiliary Clock 6 Select Status Register (MC_CGM_0_AC6_SS)............................................................813S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 19Section number Title Page23.3.33 Auxiliary Clock 6 Divider 0 Configuration Register (MC_CGM_0_AC6_DC0).......................................81423.3.34 Auxiliary Clock 7 Select Control Register (MC_CGM_0_AC7_SC)......................................................... 81523.3.35 Auxiliary Clock 7 Select Status Register (MC_CGM_0_AC7_SS)............................................................81523.3.36 Auxiliary Clock 7 Divider 1 Configuration Register (MC_CGM_0_AC7_DC1).......................................81623.3.37 Auxiliary Clock 8 Select Control Register (MC_CGM_0_AC8_SC)......................................................... 81723.3.38 Auxiliary Clock 8 Select Status Register (MC_CGM_0_AC8_SS)............................................................81823.3.39 Auxiliary Clock 8 Divider 0 Configuration Register (MC_CGM_0_AC8_DC0).......................................81923.3.40 Auxiliary Clock 8 Divider 1 Configuration Register (MC_CGM_0_AC8_DC1).......................................81923.3.41 Auxiliary Clock 9 Select Control Register (MC_CGM_0_AC9_SC)......................................................... 82023.3.42 Auxiliary Clock 9 Select Status Register (MC_CGM_0_AC9_SS)............................................................82123.3.43 Auxiliary Clock 9 Divider 0 Configuration Register (MC_CGM_0_AC9_DC0).......................................82223.3.44 Auxiliary Clock 9 Divider 1 Configuration Register (MC_CGM_0_AC9_DC1).......................................82323.3.45 Auxiliary Clock 10 Select Control Register (MC_CGM_0_AC10_SC)..................................................... 82423.3.46 Auxiliary Clock 10 Select Status Register (MC_CGM_0_AC10_SS)........................................................82523.3.47 Auxiliary Clock 10 Divider 0 Configuration Register (MC_CGM_0_AC10_DC0)...................................82523.3.48 Auxiliary Clock 10 Divider 1 Configuration Register (MC_CGM_0_AC10_DC1)...................................82623.3.49 Auxiliary Clock 11 Select Control Register (MC_CGM_0_AC11_SC)..................................................... 82723.3.50 Auxiliary Clock 11 Select Status Register (MC_CGM_0_AC11_SS)........................................................82823.3.51 Auxiliary Clock 11 Divider 0 Configuration Register (MC_CGM_0_AC11_DC0)...................................82923.3.52 Auxiliary Clock 12 Select Control Register (MC_CGM_0_AC12_SC)..................................................... 83023.3.53 Auxiliary Clock 12 Select Status Register (MC_CGM_0_AC12_SS)........................................................83123.3.54 Auxiliary Clock 12 Divider 0 Configuration Register (MC_CGM_0_AC12_DC0)...................................83123.3.55 Auxiliary Clock 13 Select Control Register (MC_CGM_0_AC13_SC)..................................................... 83223.3.56 Auxiliary Clock 13 Select Status Register (MC_CGM_0_AC13_SS)........................................................83323.3.57 Auxiliary Clock 13 Divider 0 Configuration Register (MC_CGM_0_AC13_DC0)...................................83423.3.58 Auxiliary Clock 14 Select Control Register (MC_CGM_0_AC14_SC)..................................................... 83523.3.59 Auxiliary Clock 14 Select Status Register (MC_CGM_0_AC14_SS)........................................................83623.3.60 Auxiliary Clock 14 Divider 0 Configuration Register (MC_CGM_0_AC14_DC0)...................................83723.3.61 Auxiliary Clock 15 Select Control Register (MC_CGM_0_AC15_SC)..................................................... 838S32V234 Reference Manual, Rev. 5, 11/201920 NXP SemiconductorsSection number Title Page23.3.62 Auxiliary Clock 15 Select Status Register (MC_CGM_0_AC15_SS)........................................................83923.3.63 Auxiliary Clock 15 Divider 0 Configuration Register (MC_CGM_0_AC15_DC0)...................................83923.4 MC_CGM_1 registers...................................................................................................................................................84023.4.1 PCS Switch Duration Register (MC_CGM_1_PCS_SDUR)...................................................................... 84123.4.2 PCS Divider Change Register 2 (MC_CGM_1_PCS_DIVC2)...................................................................84123.4.3 PCS Divider End Register 2 (MC_CGM_1_PCS_DIVE2).........................................................................84223.4.4 PCS Divider Start Register 2 (MC_CGM_1_PCS_DIVS2)........................................................................ 84323.4.5 Divider Update Type Register (MC_CGM_1_DIV_UPD_TYPE)............................................................. 84323.4.6 Divider Update Trigger Register (MC_CGM_1_DIV_UPD_TRIG).......................................................... 84423.4.7 Divider Update Status Register (MC_CGM_1_DIV_UPD_STAT)............................................................84523.4.8 System Clock Select Status Register (MC_CGM_1_SC_SS)..................................................................... 84623.4.9 System Clock Divider 0 Configuration Register (MC_CGM_1_SC_DC0)................................................84823.4.10 System Clock Divider 1 Configuration Register (MC_CGM_1_SC_DC1)................................................84923.4.11 System Clock Divider 2 Configuration Register (MC_CGM_1_SC_DC2)................................................85023.5 MC_CGM_2 registers...................................................................................................................................................85123.5.1 PCS Switch Duration Register (MC_CGM_2_PCS_SDUR)...................................................................... 85223.5.2 PCS Divider Change Register 2 (MC_CGM_2_PCS_DIVC2)...................................................................85223.5.3 PCS Divider End Register 2 (MC_CGM_2_PCS_DIVE2).........................................................................85323.5.4 PCS Divider Start Register 2 (MC_CGM_2_PCS_DIVS2)........................................................................ 85423.5.5 Divider Update Type Register (MC_CGM_2_DIV_UPD_TYPE)............................................................. 85423.5.6 Divider Update Trigger Register (MC_CGM_2_DIV_UPD_TRIG).......................................................... 85523.5.7 Divider Update Status Register (MC_CGM_2_DIV_UPD_STAT)............................................................85623.5.8 System Clock Select Status Register (MC_CGM_2_SC_SS)..................................................................... 85723.5.9 System Clock Divider 0 Configuration Register (MC_CGM_2_SC_DC0)................................................85923.5.10 Auxiliary Clock 0 Select Control Register (MC_CGM_2_AC0_SC)......................................................... 86023.5.11 Auxiliary Clock 0 Select Status Register (MC_CGM_2_AC0_SS)............................................................86123.5.12 Auxiliary Clock 0 Divider 0 Configuration Register (MC_CGM_2_AC0_DC0).......................................86123.5.13 Auxiliary Clock 2 Select Control Register (MC_CGM_2_AC2_SC)......................................................... 86223.5.14 Auxiliary Clock 2 Select Status Register (MC_CGM_2_AC2_SS)............................................................863S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 21Section number Title Page23.5.15 Auxiliary Clock 2 Divider 0 Configuration Register (MC_CGM_2_AC2_DC0).......................................86423.5.16 Auxiliary Clock 3 Select Control Register (MC_CGM_2_AC3_SC)......................................................... 86523.5.17 Auxiliary Clock 3 Select Status Register (MC_CGM_2_AC3_SS)............................................................86523.5.18 Auxiliary Clock 3 Divider 0 Configuration Register (MC_CGM_2_AC3_DC0).......................................86623.5.19 Auxiliary Clock 4 Select Control Register (MC_CGM_2_AC4_SC)......................................................... 86723.5.20 Auxiliary Clock 4 Select Status Register (MC_CGM_2_AC4_SS)............................................................86823.5.21 Auxiliary Clock 4 Divider 0 Configuration Register (MC_CGM_2_AC4_DC0).......................................86923.6 MC_CGM_3 registers...................................................................................................................................................87023.6.1 PCS Switch Duration Register (MC_CGM_3_PCS_SDUR)...................................................................... 87123.6.2 PCS Divider Change Register 2 (MC_CGM_3_PCS_DIVC2)...................................................................87123.6.3 PCS Divider End Register 2 (MC_CGM_3_PCS_DIVE2).........................................................................87223.6.4 PCS Divider Start Register 2 (MC_CGM_3_PCS_DIVS2)........................................................................ 87323.6.5 Divider Update Type Register (MC_CGM_3_DIV_UPD_TYPE)............................................................. 87323.6.6 Divider Update Trigger Register (MC_CGM_3_DIV_UPD_TRIG).......................................................... 87423.6.7 Divider Update Status Register (MC_CGM_3_DIV_UPD_STAT)............................................................87523.6.8 System Clock Select Status Register (MC_CGM_3_SC_SS)..................................................................... 87623.6.9 System Clock Divider 0 Configuration Register (MC_CGM_3_SC_DC0)................................................87823.6.10 System Clock Divider 1 Configuration Register (MC_CGM_3_SC_DC1)................................................87923.7 Functional description...................................................................................................................................................88023.7.1 System clock generation.............................................................................................................................. 88023.7.2 Dividers functional description....................................................................................................................88423.7.3 Aux Divider Programming...........................................................................................................................887Chapter 24PLL Digital Interface (PLLDIG)24.1 Introduction...................................................................................................................................................................88924.2 Block Diagram..............................................................................................................................................................88924.3 Features.........................................................................................................................................................................88924.4 Modes of operation....................................................................................................................................................... 88924.4.1 Normal mode with reference, PLL enabled................................................................................................. 890S32V234 Reference Manual, Rev. 5, 11/201922 NXP SemiconductorsSection number Title Page24.5 Memory map and register definition.............................................................................................................................89024.5.1 PLLDIG PLL Control Register (PLLDIG_PLLCR)................................................................................... 89124.5.2 PLLDIG PLL Status Register (PLLDIG_PLLSR)...................................................................................... 89324.5.3 PLLDIG PLL Divider Register (PLLDIG_PLLDV)................................................................................... 89524.5.4 PLLDIG PLL Frequency Modulation Register (PLLDIG_PLLFM)...........................................................89724.5.5 PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD)....................................................................89924.5.6 PLL Calibration Register 1 (PLLDIG_PLLCAL1)..................................................................................... 90124.6 Functional description...................................................................................................................................................90224.6.1 Input clock frequency...................................................................................................................................90224.6.2 Clock configuration......................................................................................................................................90224.6.3 Loss of lock..................................................................................................................................................90324.6.4 Frequency modulation..................................................................................................................................90324.7 Initialization information.............................................................................................................................................. 905Chapter 25Digital Frequency Synthesizer (DFS)25.1 Introduction...................................................................................................................................................................90725.2 Features.........................................................................................................................................................................90725.3 Memory map and register definition.............................................................................................................................90725.3.1 DFS DLL Program Register 1 (DFS_DLLPRG1).......................................................................................90825.3.2 DFS Clockout Enable Register (DFS_CLKOUTEN)..................................................................................91025.3.3 DFS Port Status Register (DFS_PORTSR)................................................................................................. 91025.3.4 DFS Port Loss of Lock Status Register (DFS_PORTLOLSR)....................................................................91125.3.5 DFS Port Reset register (DFS_PORTRESET)............................................................................................ 91125.3.6 DFS Control Register (DFS_CTRL)............................................................................................................91225.3.7 DFS Divide Register Portn (DFS_DVPORTn)........................................................................................... 91325.4 Functional Description..................................................................................................................................................913Chapter 26Fast OSC Digital Interface (FXOSC)26.1 Introduction...................................................................................................................................................................915S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 23Section number Title Page26.2 Functional description...................................................................................................................................................91526.2.1 Oscillator startup delay................................................................................................................................ 91626.2.2 Oscillator clock available interrupt.............................................................................................................. 91626.2.3 Oscillator bypass mode................................................................................................................................ 91626.3 Memory map and register definition.............................................................................................................................91726.3.1 FXOSC Control Register (FXOSC_CTL)................................................................................................... 917Chapter 27Clock Monitor Unit (CMU)27.1 Introduction...................................................................................................................................................................92127.1.1 Main features................................................................................................................................................92227.2 Block diagram...............................................................................................................................................................92227.3 Signals...........................................................................................................................................................................92227.4 Register description and memory map......................................................................................................................... 92327.4.1 CMU Control Status Register (CMU_CSR)................................................................................................92427.4.2 CMU Frequency Display Register (CMU_FDR)........................................................................................ 92527.4.3 CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)...................................................92627.4.4 CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR)....................................................92627.4.5 CMU Interrupt Status Register (CMU_ISR)............................................................................................... 92727.4.6 CMU Measurement Duration Register (CMU_MDR)................................................................................ 92827.5 Functional description...................................................................................................................................................92927.5.1 Frequency meter...........................................................................................................................................92927.5.2 CLKMN0_RMT supervisor.........................................................................................................................92927.5.3 CLKMN1 supervisor....................................................................................................................................930Chapter 28Reset Overview28.1 Introduction...................................................................................................................................................................93328.1.1 Global Reset.................................................................................................................................................93328.1.2 Local Reset...................................................................................................................................................93328.1.3 Reset sources................................................................................................................................................933S32V234 Reference Manual, Rev. 5, 11/201924 NXP SemiconductorsSection number Title Page28.2 Global Reset Process.....................................................................................................................................................93528.2.1 Overview......................................................................................................................................................93528.2.2 Reset Process Modules.................................................................................................................................93528.2.3 Reset Process Sequences..............................................................................................................................93828.2.4 Reset Process State Transitions....................................................................................................................93928.2.5 Module Status During Reset Process........................................................................................................... 948Chapter 29System Reset Controller (SRC)29.1 Overview.......................................................................................................................................................................94929.2 Memory map and register definition.............................................................................................................................94929.2.1 Boot Mode Register 1 (SRC_BMR1).......................................................................................................... 95129.2.2 Boot Mode Register 2 (SRC_BMR2).......................................................................................................... 95129.2.3 General Purpose Register 1 For Boot (SRC_GPR1_BOOT).......................................................................95329.2.4 General Purpose Register 1 (SRC_GPR1)...................................................................................................95429.2.5 General Purpose Register 2 (SRC_GPR2)...................................................................................................95529.2.6 General Purpose Register 3 (SRC_GPR3)...................................................................................................95629.2.7 General Purpose Register 4 (SRC_GPR4)...................................................................................................95829.2.8 General Purpose Register 5 (SRC_GPR5)...................................................................................................95829.2.9 General Purpose Register 6 (SRC_GPR6)...................................................................................................96129.2.10 General Purpose Register 8 (SRC_GPR8)...................................................................................................96329.2.11 General Purpose Register 10 (SRC_GPR10)...............................................................................................96429.2.12 General Purpose Register 11 (SRC_GPR11)...............................................................................................96529.2.13 General Purpose Register 12 (SRC_GPR12)...............................................................................................96729.2.14 General Purpose Register 13 (SRC_GPR13)...............................................................................................96829.2.15 General Purpose Register 14 (SRC_GPR14)...............................................................................................97029.2.16 General Purpose Register 15 (SRC_GPR15)...............................................................................................97229.2.17 General Purpose Register 16 (SRC_GPR16)...............................................................................................97329.2.18 General Purpose Register 18 (SRC_GPR18)...............................................................................................97529.2.19 General Purpose Register 19 (SRC_GPR19)...............................................................................................975S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 25Section number Title Page29.2.20 General Purpose Register 20 (SRC_GPR20)...............................................................................................97629.2.21 General Purpose Register 21 (SRC_GPR21)...............................................................................................97629.2.22 General Purpose Register 22 (SRC_GPR22)...............................................................................................97729.2.23 DDR_MEMORY_ACCESS_SECURE (SRC_GPR23)..............................................................................97729.2.24 DDR_MEMORY_ACCESS_NON_SECURE (SRC_GPR24)................................................................... 97729.2.25 SRAM_MEMORY_ACCESS_SECURE (SRC_GPR25)...........................................................................97829.2.26 SRAM_MEMORY_ACCESS_NON_SECURE (SRC_GPR26)................................................................ 97829.2.27 SELFTEST CONFIGURATION REGISTER (SRC_GPR27)....................................................................97929.2.28 PCIe Configuration1 register (SRC_PCIE_CONFIG_1)............................................................................ 98029.2.29 DDR Self Refresh Control register (SRC_DDR_SELF_REF_CTRL)........................................................98329.2.30 PCIe Configuration0 register (SRC_PCIE_CONFIG_0)............................................................................ 98529.2.31 SOC_MISC_CONFIG REGISTER 2 (SRC_SOC_MISC_CONFIG2)...................................................... 987Chapter 30System Boot30.1 Introduction...................................................................................................................................................................98930.2 Boot Modes...................................................................................................................................................................99030.2.1 Boot vector in AARCH64 (default mode)................................................................................................... 99030.2.2 Boot Modes Pin Settings..............................................................................................................................99130.2.3 High Level Boot Sequence.......................................................................................................................... 99130.2.4 Boot from Fuses........................................................................................................................................... 99430.2.5 Serial Download Mode................................................................................................................................ 99430.2.6 Boot from RCON......................................................................................................................................... 99430.3 Device Configuration....................................................................................................................................................99530.3.1 Boot eFuse Descriptions.............................................................................................................................. 99530.3.2 GPIO Boot Config Select.............................................................................................................................99730.4 Device Initialization......................................................................................................................................................99830.4.1 Internal ROM and RAM Memory Map....................................................................................................... 99930.4.2 Boot block activation................................................................................................................................... 100130.4.3 Clocks at boot time...................................................................................................................................... 1001S32V234 Reference Manual, Rev. 5, 11/201926 NXP SemiconductorsSection number Title Page30.4.4 Enabling Caches...........................................................................................................................................100230.4.5 Error Logging...............................................................................................................................................100230.4.6 Exception Handling......................................................................................................................................100530.4.7 Interrupt Handling........................................................................................................................................100630.4.8 NMI Handling.............................................................................................................................................. 100630.4.9 Fast Reboot.................................................................................................................................................. 100630.5 Boot Device (Internal Boot)..........................................................................................................................................100730.5.1 QuadSPI Serial Flash Memory Boot............................................................................................................100730.5.2 Expansion Device (SD/MMC/eMMC) Boot............................................................................................... 101530.6 Program Image..............................................................................................................................................................102630.6.1 Image Vector Table and Boot Data..............................................................................................................102630.6.2 Device Configuration Data.......................................................................................................................... 102830.6.3 Self Test Image............................................................................................................................................ 103430.7 Serial Downloader........................................................................................................................................................ 103530.7.1 Serial Download Protocol............................................................................................................................ 103630.7.2 FlexCAN Boot............................................................................................................................................. 103830.7.3 UART Boot.................................................................................................................................................. 103930.8 Application Boot...........................................................................................................................................................104030.8.1 Boot Cortex-A53[0] Mode...........................................................................................................................104130.8.2 Application boot address validation.............................................................................................................1042Chapter 31Reset Generation Module (MC_RGM)31.1 Introduction...................................................................................................................................................................104331.1.1 Overview......................................................................................................................................................104331.1.2 Features........................................................................................................................................................ 104431.1.3 Reset Sources............................................................................................................................................... 104531.2 External signal description............................................................................................................................................104631.3 Memory map and register definition.............................................................................................................................104731.3.1 'Destructive' Event Status Register (MC_RGM_DES)................................................................................1048S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 27Section number Title Page31.3.2 'Functional' Event Status Register (MC_RGM_FES)..................................................................................105031.3.3 'Functional' Event Reset Disable Register (MC_RGM_FERD).................................................................. 105231.3.4 'Functional' Bidirectional Reset Enable Register (MC_RGM_FBRE)........................................................105331.3.5 Functional' Event Short Sequence Register (MC_RGM_FESS)................................................................. 105531.3.6 DDR Handshake Enable Register (MC_RGM_DDR_HE)......................................................................... 105731.3.7 DDR Handshake Status Register (MC_RGM_DDR_HS)...........................................................................105931.3.8 Functional Reset Handshake Enable (MC_RGM_FRHE)...........................................................................106031.3.9 Functional Reset Escalation Counter (MC_RGM_FREC).......................................................................... 106131.3.10 'Functional' Reset Escalation Threshold Register (MC_RGM_FRET)....................................................... 106231.3.11 'Destructive' Reset Escalation Threshold Register (MC_RGM_DRET)..................................................... 106331.4 Functional description...................................................................................................................................................106331.4.1 Reset state machine......................................................................................................................................106331.4.2 'Destructive' resets........................................................................................................................................106631.4.3 Bi-directional External reset........................................................................................................................ 106731.4.4 'Functional' resets......................................................................................................................................... 106731.4.5 'Functional' reset escalation..........................................................................................................................106831.4.6 'Destructive' reset escalation........................................................................................................................ 1068Chapter 32On-Chip One Time Programmable (OCOTP) Controller32.1 Introduction...................................................................................................................................................................107132.2 Overview of On-Chip OTP (OCOTP) controller..........................................................................................................107132.3 Top-level symbol and functional overview.................................................................................................................. 107232.3.1 Operation......................................................................................................................................................107232.3.2 OTP read/write timing parameters...............................................................................................................107832.3.3 Behavior During Reset.................................................................................................................................107932.4 Memory map and register definition.............................................................................................................................107932.4.1 OTP Controller Control Register (OCOTP_CTRLn).................................................................................. 108532.4.2 OTP Controller Timing Register (OCOTP_TIMING)................................................................................ 108732.4.3 OTP Controller Write Data Register (OCOTP_DATA)..............................................................................1088S32V234 Reference Manual, Rev. 5, 11/201928 NXP SemiconductorsSection number Title Page32.4.4 OTP Controller Read Control Register (OCOTP_READ_CTRL).............................................................. 108932.4.5 OTP Controller Read Data Register (OCOTP_READ_FUSE_DATA)...................................................... 109032.4.6 Sticky bit Register (OCOTP_SW_STICKY)...............................................................................................109032.4.7 OTP Controller CRC test address (OCOTP_CRC_ADDR)........................................................................ 109132.4.8 OTP Controller CRC Value Register (OCOTP_CRC_VALUE)................................................................ 109132.4.9 OTP Controller Version Register (OCOTP_VERSION).............................................................................109232.4.10 Value of OTP Bank4 Word2 (MAC Address0) (OCOTP_MAC0).............................................................109232.4.11 Value of OTP Bank4 Word3 (MAC Address) (OCOTP_MAC1)...............................................................109332.4.12 Value of OTP Bank4 Word6 (HW Capabilities) (OCOTP_GP1)............................................................... 109332.4.13 Value of OTP Bank4 Word7 (HW Capabilities) (OCOTP_GP2)............................................................... 109432.4.14 Value of OTP Bank5 Word2 (OCOTP_MISC_CONF).............................................................................. 109432.4.15 Value of OTP Bank5 Word3 (OCOTP_FIELD_RTN)................................................................................109532.4.16 Value of OTP Bank5 Word4 (OCOTP_MISC2)......................................................................................... 109632.4.17 Value of OTP Bank5 Word5 (CRC0) (OCOTP_CRC0)............................................................................. 109632.4.18 Value of OTP Bank5 Word6 (CRC1) (OCOTP_CRC1)............................................................................. 109632.4.19 Value of OTP Bank5 Word7 (CRC2) (OCOTP_CRC2)............................................................................. 109732.4.20 Value of OTP Bank6 Word0 (CRC3) (OCOTP_CRC3)............................................................................. 109732.4.21 Value of OTP Bank6 Word1 (CRC4) (OCOTP_CRC4)............................................................................. 109832.4.22 Value of OTP Bank6 Word2 (CRC5) (OCOTP_CRC5)............................................................................. 109832.4.23 ECC Fuse words (OCOTP_ECC_FUSEn).................................................................................................. 109932.4.24 Redundant Fuse words (OCOTP_REDUNDANT_FUSEn)........................................................................109932.4.25 Single Bit ECC Error status (OCOTP_SEC0)............................................................................................. 110032.4.26 Single Bit ECC Error status (OCOTP_SEC1)............................................................................................. 110132.4.27 Single Bit ECC Error status (OCOTP_DEC0)............................................................................................ 110232.4.28 Double Bit ECC Error status (OCOTP_DEC1)...........................................................................................1103Chapter 33Quad Serial Peripheral Interface (QuadSPI)33.1 Introduction...................................................................................................................................................................110533.1.1 Features........................................................................................................................................................ 1105S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 29Section number Title Page33.1.2 Block Diagram............................................................................................................................................. 110633.1.3 QuadSPI Modes of Operation...................................................................................................................... 110733.1.4 Acronyms and Abbreviations.......................................................................................................................110833.1.5 Glossary for QuadSPI module..................................................................................................................... 110833.2 External Signal Description.......................................................................................................................................... 111033.2.1 Driving External Signals..............................................................................................................................111133.3 Memory Map and Register Definition..........................................................................................................................111333.3.1 Register Write Access..................................................................................................................................111333.3.2 Peripheral Bus Register Descriptions.......................................................................................................... 111433.3.3 Serial Flash Address Assignment................................................................................................................ 115833.3.4 AMBA Bus Register Memory Map............................................................................................................. 115833.3.5 AHB Bus Register Memory Map Descriptions........................................................................................... 116033.4 Interrupt Signals............................................................................................................................................................116633.5 Functional Description..................................................................................................................................................116733.5.1 Serial Flash Access Schemes....................................................................................................................... 116733.5.2 Modes of Operation..................................................................................................................................... 116833.5.3 Normal Mode............................................................................................................................................... 116833.6 Initialization/Application Information..........................................................................................................................119133.6.1 Power Up and Reset.....................................................................................................................................119133.6.2 Available Status/Flag Information............................................................................................................... 119133.6.3 Exclusive Access to Serial Flash for AHB Commands............................................................................... 119433.6.4 Command Arbitration ................................................................................................................................. 119533.6.5 Flash Device Selection.................................................................................................................................119633.6.6 DMA Usage................................................................................................................................................. 119633.6.7 Parallel mode................................................................................................................................................120033.7 Byte Ordering - Endianness..........................................................................................................................................120233.7.1 Programming Flash Data............................................................................................................................. 120333.7.2 Reading Flash Data into the RX Buffer....................................................................................................... 120433.7.3 Reading Flash Data into the AHB Buffer.................................................................................................... 1205S32V234 Reference Manual, Rev. 5, 11/201930 NXP SemiconductorsSection number Title Page33.8 Serial Flash Devices......................................................................................................................................................120533.8.1 Example Sequences......................................................................................................................................120533.8.2 Dual Die Flashes.......................................................................................................................................... 121133.8.3 Boot initialization sequence......................................................................................................................... 121233.9 Sampling of Serial Flash Input Data.............................................................................................................................121333.9.1 Basic Description......................................................................................................................................... 121333.9.2 Supported read modes..................................................................................................................................121433.9.3 Data Strobe (DQS) sampling method.......................................................................................................... 121533.10 Data Input Hold Requirement of Flash.........................................................................................................................1220Chapter 34Multi Mode DDR Controller (MMDC)34.1 Chip-specific MMDC information............................................................................................................................... 122334.1.1 MMDC Configuration..................................................................................................................................122334.1.2 MMDC Core AXI Re-ordering Control Register (MAARCR) Settings..................................................... 122434.1.3 DDR memory contents retention on a functional reset................................................................................122434.1.4 DDR memory contents retention across selftest.......................................................................................... 122534.1.5 MASTER AXI ID programming for using MMDC profiling feature......................................................... 122634.2 Overview.......................................................................................................................................................................122734.2.1 MMDC feature summary............................................................................................................................. 122834.3 External Signals............................................................................................................................................................ 123134.4 Functional Description..................................................................................................................................................123134.4.1 Write/Read data flow................................................................................................................................... 123134.4.2 MMDC initialization ...................................................................................................................................123334.4.3 Configuring the MMDC registers................................................................................................................ 123434.4.4 MMDC Address Space................................................................................................................................ 123534.4.5 LPDDR2 and DDR3 pin mux mapping....................................................................................................... 124034.4.6 Power Saving and Clock Frequency Change modes................................................................................... 124134.4.7 Reset ............................................................................................................................................................124334.4.8 Refresh Scheme............................................................................................................................................1244S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 31Section number Title Page34.4.9 Burst Length options towards DDR ............................................................................................................124534.4.10 Exclusive accesses handling........................................................................................................................ 124634.4.11 AXI Error Handling..................................................................................................................................... 124734.5 Performance.................................................................................................................................................................. 124734.5.1 Arbitration and reordering mechanism........................................................................................................ 124734.5.2 Prediction mechanism.................................................................................................................................. 125034.5.3 Special Optimization for accesses towards DDR3...................................................................................... 125034.6 MMDC Debug ............................................................................................................................................................. 125134.6.1 Hardware debug monitor............................................................................................................................. 125134.6.2 Step By Step (SBS) software monitor..........................................................................................................125134.7 MMDC Profiling...........................................................................................................................................................125234.8 LPDDR2 Refresh Rate Update and Timing Derating...................................................................................................125334.9 DLL Off mode.............................................................................................................................................................. 125434.10 ODT Configuration ......................................................................................................................................................125534.11 Calibration Process....................................................................................................................................................... 125634.11.1 Delay-line.....................................................................................................................................................125734.11.2 ZQ calibration ............................................................................................................................................. 125834.11.3 Read DQS Gating Calibration......................................................................................................................126134.11.4 Read Calibration.......................................................................................................................................... 126734.11.5 Write Calibration..........................................................................................................................................127234.11.6 Write leveling Calibration............................................................................................................................127534.11.7 Read fine tuning........................................................................................................................................... 127934.12 MMDC Memory Map/Register Definition...................................................................................................................127934.12.1 MMDC Core Control Register (MMDC_MDCTL).................................................................................... 128334.12.2 MMDC Core Power Down Control Register (MMDC_MDPDC).............................................................. 128434.12.3 MMDC Core ODT Timing Control Register (MMDC_MDOTC)..............................................................128734.12.4 MMDC Core Timing Configuration Register 0 (MMDC_MDCFG0)........................................................ 128834.12.5 MMDC Core Timing Configuration Register 1 (MMDC_MDCFG1)........................................................ 129034.12.6 MMDC Core Timing Configuration Register 2 (MMDC_MDCFG2)........................................................ 1293S32V234 Reference Manual, Rev. 5, 11/201932 NXP SemiconductorsSection number Title Page34.12.7 MMDC Core Miscellaneous Register (MMDC_MDMISC)....................................................................... 129534.12.8 MMDC Core Special Command Register (MMDC_MDSCR)................................................................... 129834.12.9 MMDC Core Refresh Control Register (MMDC_MDREF)....................................................................... 130134.12.10 MMDC Core Read/Write Command Delay Register (MMDC_MDRWD)................................................ 130334.12.11 MMDC Core Out of Reset Delays Register (MMDC_MDOR).................................................................. 130534.12.12 MMDC Core MRR Data Register (MMDC_MDMRR)..............................................................................130634.12.13 MMDC Core Timing Configuration Register 3 (MMDC_MDCFG3LP)................................................... 130734.12.14 MMDC Core MR4 Derating Register (MMDC_MDMR4).........................................................................130934.12.15 MMDC Core Address Space Partition Register (MMDC_MDASP).......................................................... 131034.12.16 MMDC Core AXI Reordering Control Regsiter (MMDC_MAARCR)......................................................131134.12.17 MMDC Core Power Saving Control and Status Register (MMDC_MAPSR)............................................131434.12.18 MMDC Core Exclusive ID Monitor Register0 (MMDC_MAEXIDR0).....................................................131634.12.19 MMDC Core Exclusive ID Monitor Register1 (MMDC_MAEXIDR1).....................................................131734.12.20 MMDC Core Debug and Profiling Control Register 0 (MMDC_MADPCR0)...........................................131834.12.21 MMDC Core Debug and Profiling Control Register 1 (MMDC_MADPCR1)...........................................131934.12.22 MMDC Core Debug and Profiling Status Register 0 (MMDC_MADPSR0)..............................................132034.12.23 MMDC Core Debug and Profiling Status Register 1 (MMDC_MADPSR1)..............................................132034.12.24 MMDC Core Debug and Profiling Status Register 2 (MMDC_MADPSR2)..............................................132134.12.25 MMDC Core Debug and Profiling Status Register 3 (MMDC_MADPSR3)..............................................132134.12.26 MMDC Core Debug and Profiling Status Register 4 (MMDC_MADPSR4)..............................................132234.12.27 MMDC Core Debug and Profiling Status Register 5 (MMDC_MADPSR5)..............................................132234.12.28 MMDC Core Step By Step Address Register (MMDC_MASBS0)............................................................ 132334.12.29 MMDC Core Step By Step Address Attributes Register (MMDC_MASBS1)........................................... 132334.12.30 MMDC Core General Purpose Register (MMDC_MAGENP)................................................................... 132434.12.31 MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL).......................................................... 132534.12.32 MMDC PHY ZQ SW control register (MMDC_MPZQSWCTRL)............................................................132834.12.33 MMDC PHY Write Leveling Configuration and Error Status Register (MMDC_MPWLGCR)............... 133034.12.34 MMDC PHY Write Leveling Delay Control Register 0 (MMDC_MPWLDECTRL0)..............................133334.12.35 MMDC PHY Write Leveling Delay Control Register 1 (MMDC_MPWLDECTRL1)..............................1335S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 33Section number Title Page34.12.36 MMDC PHY Write Leveling delay-line Status Register (MMDC_MPWLDLST).................................... 133834.12.37 MMDC PHY ODT control register (MMDC_MPODTCTRL)...................................................................133934.12.38 MMDC PHY Read DQ Byte0 Delay Register (MMDC_MPRDDQBY0DL)............................................ 134134.12.39 MMDC PHY Read DQ Byte1 Delay Register (MMDC_MPRDDQBY1DL)............................................ 134434.12.40 MMDC PHY Read DQ Byte2 Delay Register (MMDC_MPRDDQBY2DL)............................................ 134734.12.41 MMDC PHY Read DQ Byte3 Delay Register (MMDC_MPRDDQBY3DL)............................................ 134934.12.42 MMDC PHY Read DQS Gating Control Register 0 (MMDC_MPDGCTRL0)......................................... 135234.12.43 MMDC PHY Read DQS Gating Control Register 1 (MMDC_MPDGCTRL1)......................................... 135434.12.44 MMDC PHY Read DQS Gating delay-line Status Register (MMDC_MPDGDLST0)..............................135734.12.45 MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL)....................................135834.12.46 MMDC PHY Read delay-lines Status Register (MMDC_MPRDDLST)................................................... 136034.12.47 MMDC PHY Write delay-lines Configuration Register (MMDC_MPWRDLCTL).................................. 136134.12.48 MMDC PHY Write delay-lines Status Register (MMDC_MPWRDLST)..................................................136234.12.49 MMDC ZQ LPDDR2 HW Control Register (MMDC_MPZQLP2CTL)....................................................136334.12.50 MMDC PHY Read Delay HW Calibration Control Register (MMDC_MPRDDLHWCTL).....................136534.12.51 MMDC PHY Write Delay HW Calibration Control Register (MMDC_MPWRDLHWCTL)................... 136734.12.52 MMDC PHY Read Delay HW Calibration Status Register 0 (MMDC_MPRDDLHWST0)..................... 136834.12.53 MMDC PHY Read Delay HW Calibration Status Register 1 (MMDC_MPRDDLHWST1)..................... 136934.12.54 MMDC PHY Write Delay HW Calibration Status Register 0 (MMDC_MPWRDLHWST0)................... 137034.12.55 MMDC PHY Write Delay HW Calibration Status Register 1 (MMDC_MPWRDLHWST1)................... 137134.12.56 MMDC PHY Write Leveling HW Error Register (MMDC_MPWLHWERR).......................................... 137234.12.57 MMDC PHY Read DQS Gating HW Status Register 0 (MMDC_MPDGHWST0)...................................137234.12.58 MMDC PHY Read DQS Gating HW Status Register 1 (MMDC_MPDGHWST1)...................................137334.12.59 MMDC PHY Read DQS Gating HW Status Register 2 (MMDC_MPDGHWST2)...................................137334.12.60 MMDC PHY Read DQS Gating HW Status Register 3 (MMDC_MPDGHWST3)...................................137434.12.61 MMDC PHY Pre-defined Compare Register 1 (MMDC_MPPDCMPR1)................................................. 137534.12.62 MMDC PHY Pre-defined Compare and CA delay-line Configuration Register(MMDC_MPPDCMPR2)............................................................................................................................ 137634.12.63 MMDC PHY SW Dummy Access Register (MMDC_MPSWDAR0)........................................................1378S32V234 Reference Manual, Rev. 5, 11/201934 NXP SemiconductorsSection number Title Page34.12.64 MMDC PHY SW Dummy Read Data Register 0 (MMDC_MPSWDRDR0).............................................137934.12.65 MMDC PHY SW Dummy Read Data Register 1 (MMDC_MPSWDRDR1).............................................138034.12.66 MMDC PHY SW Dummy Read Data Register 2 (MMDC_MPSWDRDR2).............................................138034.12.67 MMDC PHY SW Dummy Read Data Register 3 (MMDC_MPSWDRDR3).............................................138034.12.68 MMDC PHY SW Dummy Read Data Register 4 (MMDC_MPSWDRDR4).............................................138134.12.69 MMDC PHY SW Dummy Read Data Register 5 (MMDC_MPSWDRDR5).............................................138134.12.70 MMDC PHY SW Dummy Read Data Register 6 (MMDC_MPSWDRDR6).............................................138234.12.71 MMDC PHY SW Dummy Read Data Register 7 (MMDC_MPSWDRDR7).............................................138234.12.72 MMDC PHY Measure Unit Register (MMDC_MPMUR0)........................................................................138334.12.73 MMDC Duty Cycle Control Register (MMDC_MPDCCR)....................................................................... 1384Chapter 35MMDC ECC and Debug Watchpoint (MEW)35.1 Chip-specific MEW information.................................................................................................................................. 138735.2 Introduction...................................................................................................................................................................138735.3 Features.........................................................................................................................................................................138735.4 Block Diagram..............................................................................................................................................................138935.5 Memory Map................................................................................................................................................................ 139035.5.1 AXI ECC Global Control Register (MEW_AXI_ECC_GLBL_CTRL)..................................................... 139235.5.2 AXI ECC Maximum ECC protected address register (MEW_AXI_ECC_MX_EPA)............................... 139335.5.3 AXI ECC Minimum ECC protected address register (MEW_AXI_ECC_MN_EPA)................................139335.5.4 AXI ECC Lock Pattern Register (MEW_AXI_ECC_LK_PTN).................................................................139335.5.5 AXI ECC Unlock Pattern Register (MEW_AXI_ECC_ULK_PTN).......................................................... 139435.5.6 ECC Error Report Address Register (MEW_AXI_ECC_EERAR).............................................................139535.5.7 AXI ECC Error Report Data and Syndrome Register (MEW_AXI_ECC_EERDSRn)..............................139535.5.8 AXI ECC error interrupt enable (MEW_AXI_ECC_ERR_IE)...................................................................139635.5.9 AXI ECC error Interupt status and clear register (MEW_AXI_ECC_ERR_IN_STCLR)..........................139835.5.10 AXI EDC Error interrupt enable register (MEW_AXI_EDC_ERR_IE).....................................................140035.5.11 AXI EDC Error Interrupt Status and Clear register (MEW_AXI_EDC_ERR_IN_STCLR)......................140235.5.12 Shadow Control, RW path Status and Status Clear Register (MEW_AXI_ECC_SHD_STAT_CTRL).... 1403S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 35Section number Title Page35.5.13 Correctable and un-correctable bit error counter (MEW_AXI_ECC_CBL_UNCBL_BIT_EC)................140635.5.14 Correctable and un-correctable beat error counter (MEW_AXI_ECC_CBL_UCBL_BEAT_EC)............ 140835.5.15 Debug and Debug Control Register (MEW_AXI_ECC_DBG_CTRL)...................................................... 140935.6 ECC(Error Correcting Code)........................................................................................................................................ 141035.6.1 ECC Features............................................................................................................................................... 141035.6.2 Hamming code for SEC-DED-TED............................................................................................................ 141035.6.3 ECC encoder................................................................................................................................................ 141335.6.4 ECC decoder................................................................................................................................................ 141435.7 Error Injection Logic.....................................................................................................................................................141535.8 Steps to configure and use............................................................................................................................................ 141635.9 Limitations / Deviations from standard ....................................................................................................................... 141835.10 Watchpoint....................................................................................................................................................................141835.10.1 Introduction..................................................................................................................................................141835.10.2 Features........................................................................................................................................................ 141935.10.3 Detailed Description of Watchpoint............................................................................................................ 1419Chapter 36FlexTimer Module (FTM)36.1 Chip-specific FTM information....................................................................................................................................143736.1.1 Configuration............................................................................................................................................... 143736.1.2 FTM Global Time Base............................................................................................................................... 143836.1.3 FTM Trigger implmentation........................................................................................................................ 143836.1.4 ENET-FTM connection............................................................................................................................... 143936.2 Introduction...................................................................................................................................................................143936.2.1 FlexTimer philosophy.................................................................................................................................. 144036.2.2 Features........................................................................................................................................................ 144136.2.3 Modes of operation...................................................................................................................................... 144236.2.4 Block diagram.............................................................................................................................................. 144236.3 FTM signal descriptions............................................................................................................................................... 144536.4 Memory map and register definition.............................................................................................................................1445S32V234 Reference Manual, Rev. 5, 11/201936 NXP SemiconductorsSection number Title Page36.4.1 Memory map................................................................................................................................................ 144536.4.2 Register descriptions.................................................................................................................................... 144636.4.3 Status And Control (FTM_SC).................................................................................................................... 144836.4.4 Counter (FTM_CNT)...................................................................................................................................144936.4.5 Modulo (FTM_MOD)..................................................................................................................................145036.4.6 Channel (n) Status And Control (FTM_CnSC)........................................................................................... 145136.4.7 Channel (n) Value (FTM_CnV)...................................................................................................................145436.4.8 Counter Initial Value (FTM_CNTIN)..........................................................................................................145436.4.9 Capture And Compare Status (FTM_STATUS)..........................................................................................145536.4.10 Features Mode Selection (FTM_MODE).................................................................................................... 145736.4.11 Synchronization (FTM_SYNC)...................................................................................................................145836.4.12 Initial State For Channels Output (FTM_OUTINIT).................................................................................. 146136.4.13 Output Mask (FTM_OUTMASK)............................................................................................................... 146236.4.14 Function For Linked Channels (FTM_COMBINE).................................................................................... 146436.4.15 Deadtime Insertion Control (FTM_DEADTIME).......................................................................................146836.4.16 FTM External Trigger (FTM_EXTTRIG)...................................................................................................146936.4.17 Channels Polarity (FTM_POL)....................................................................................................................147136.4.18 Fault Mode Status (FTM_FMS).................................................................................................................. 147336.4.19 Input Capture Filter Control (FTM_FILTER)............................................................................................. 147436.4.20 Quadrature Decoder Control And Status (FTM_QDCTRL)....................................................................... 147536.4.21 Configuration (FTM_CONF).......................................................................................................................147736.4.22 Synchronization Configuration (FTM_SYNCONF)................................................................................... 147836.4.23 FTM Inverting Control (FTM_INVCTRL)................................................................................................. 148036.4.24 FTM Software Output Control (FTM_SWOCTRL)....................................................................................148136.4.25 FTM PWM Load (FTM_PWMLOAD)....................................................................................................... 148436.5 Functional description...................................................................................................................................................148536.5.1 Clock source.................................................................................................................................................148636.5.2 Prescaler....................................................................................................................................................... 148636.5.3 Counter.........................................................................................................................................................1487S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 37Section number Title Page36.5.4 Input Capture mode......................................................................................................................................149336.5.5 Output Compare mode................................................................................................................................. 149736.5.6 Edge-Aligned PWM (EPWM) mode........................................................................................................... 149836.5.7 Center-Aligned PWM (CPWM) mode........................................................................................................ 150036.5.8 Combine mode............................................................................................................................................. 150236.5.9 Complementary mode.................................................................................................................................. 150936.5.10 Registers updated from write buffers...........................................................................................................151036.5.11 PWM synchronization..................................................................................................................................151236.5.12 Inverting....................................................................................................................................................... 152836.5.13 Software output control................................................................................................................................152936.5.14 Deadtime insertion....................................................................................................................................... 153136.5.15 Output mask................................................................................................................................................. 153436.5.16 Polarity control.............................................................................................................................................153436.5.17 Initialization................................................................................................................................................. 153536.5.18 Features priority........................................................................................................................................... 153536.5.19 Channel trigger output................................................................................................................................. 153636.5.20 Initialization trigger......................................................................................................................................153836.5.21 Capture Test mode....................................................................................................................................... 154036.5.22 DMA............................................................................................................................................................ 154136.5.23 Dual Edge Capture mode............................................................................................................................. 154236.5.24 Quadrature Decoder mode........................................................................................................................... 154936.5.25 BDM mode...................................................................................................................................................155436.5.26 Intermediate load..........................................................................................................................................155536.5.27 Global time base (GTB)...............................................................................................................................155736.6 Reset overview..............................................................................................................................................................155836.7 FTM Interrupts..............................................................................................................................................................156036.7.1 Timer Overflow Interrupt.............................................................................................................................156036.7.2 Channel (n) Interrupt....................................................................................................................................156036.8 Initialization Procedure.................................................................................................................................................1560S32V234 Reference Manual, Rev. 5, 11/201938 NXP SemiconductorsSection number Title PageChapter 37Periodic Interrupt Timer (PIT)37.1 Chip-specific PIT information...................................................................................................................................... 156337.1.1 Overview......................................................................................................................................................156337.1.2 Configuration............................................................................................................................................... 156337.1.3 PIT Channel Assignment............................................................................................................................. 156337.1.4 PIT instances register differences................................................................................................................ 156437.2 Introduction...................................................................................................................................................................156437.2.1 Block diagram.............................................................................................................................................. 156437.2.2 Features........................................................................................................................................................ 156537.3 Signal description..........................................................................................................................................................156537.4 Memory map/register description.................................................................................................................................156637.4.1 PIT Module Control Register (PIT_MCR).................................................................................................. 156737.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)............................................................................... 156837.4.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)............................................................................... 156837.4.4 Timer Load Value Register (PIT_LDVALn)...............................................................................................156937.4.5 Current Timer Value Register (PIT_CVALn)............................................................................................. 156937.4.6 Timer Control Register (PIT_TCTRLn)...................................................................................................... 157037.4.7 Timer Flag Register (PIT_TFLGn)..............................................................................................................157137.5 Functional description...................................................................................................................................................157237.5.1 General operation.........................................................................................................................................157237.5.2 Interrupts...................................................................................................................................................... 157437.5.3 Chained timers............................................................................................................................................. 157437.6 Initialization and application information.....................................................................................................................157437.7 Example configuration for chained timers....................................................................................................................157537.8 Example configuration for the lifetime timer............................................................................................................... 1576Chapter 38Software Watchdog Timer (SWT)38.1 Chip-specific SWT information....................................................................................................................................1577S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 39Section number Title Page38.1.1 SWT chip specific information.................................................................................................................... 157738.2 Introduction...................................................................................................................................................................157838.2.1 Overview......................................................................................................................................................157838.2.2 Features........................................................................................................................................................ 157838.2.3 Modes of operation...................................................................................................................................... 157838.3 External signal description............................................................................................................................................157938.4 Memory Map and Registers..........................................................................................................................................157938.4.1 SWT Control Register (SWT_CR).............................................................................................................. 158038.4.2 SWT Interrupt Register (SWT_IR)..............................................................................................................158338.4.3 SWT Time-out Register (SWT_TO)............................................................................................................158438.4.4 SWT Window Register (SWT_WN)........................................................................................................... 158438.4.5 SWT Service Register (SWT_SR)...............................................................................................................158538.4.6 SWT Counter Output Register (SWT_CO)................................................................................................. 158538.4.7 SWT Service Key Register (SWT_SK)....................................................................................................... 158638.5 Functional description...................................................................................................................................................158638.5.1 Introduction..................................................................................................................................................158638.5.2 Configuration locking.................................................................................................................................. 158838.5.3 Unlock sequence.......................................................................................................................................... 158838.5.4 Servicing operations.....................................................................................................................................158838.5.5 Time-out.......................................................................................................................................................159038.5.6 Initialization................................................................................................................................................. 1590Chapter 39System Timer Module (STM)39.1 Chip-specific STM information....................................................................................................................................159139.1.1 STM Instances..............................................................................................................................................159139.2 Introduction...................................................................................................................................................................159139.2.1 Overview......................................................................................................................................................159139.2.2 Features........................................................................................................................................................ 159139.2.3 Modes of operation...................................................................................................................................... 1592S32V234 Reference Manual, Rev. 5, 11/201940 NXP SemiconductorsSection number Title Page39.3 External signal description............................................................................................................................................159239.4 Memory map and registers............................................................................................................................................159239.4.1 STM Control Register (STM_CR)...............................................................................................................159339.4.2 STM Count Register (STM_CNT).............................................................................................................. 159439.4.3 STM Channel Control Register (STM_CCRn)............................................................................................159439.4.4 STM Channel Interrupt Register (STM_CIRn)........................................................................................... 159539.4.5 STM Channel Compare Register (STM_CMPn).........................................................................................159639.5 Functional description...................................................................................................................................................1596Chapter 40Controller Area Network (FlexCAN)40.1 Chip-specific FlexCAN information.............................................................................................................................159740.1.1 FlexCAN Configurations............................................................................................................................. 159740.1.2 Requirements for entering FlexCAN modes: Freeze, Module Disable, Stop..............................................159840.2 Introduction...................................................................................................................................................................159940.2.1 Overview......................................................................................................................................................160040.2.2 FlexCAN module features........................................................................................................................... 160140.2.3 Modes of operation...................................................................................................................................... 160340.3 FlexCAN signal descriptions........................................................................................................................................ 160540.3.1 CAN Rx .......................................................................................................................................................160540.3.2 CAN Tx .......................................................................................................................................................160540.4 Memory map/register definition................................................................................................................................... 160540.4.1 FlexCAN memory mapping.........................................................................................................................160540.4.2 Module Configuration Register (CAN_MCR)............................................................................................ 161240.4.3 Control 1 register (CAN_CTRL1)............................................................................................................... 161640.4.4 Free Running Timer (CAN_TIMER).......................................................................................................... 162040.4.5 Rx Mailboxes Global Mask Register (CAN_RXMGMASK)..................................................................... 162140.4.6 Rx 14 Mask register (CAN_RX14MASK)..................................................................................................162340.4.7 Rx 15 Mask register (CAN_RX15MASK)..................................................................................................162340.4.8 Error Counter (CAN_ECR)......................................................................................................................... 1624S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 41Section number Title Page40.4.9 Error and Status 1 register (CAN_ESR1).................................................................................................... 162640.4.10 Interrupt Masks 2 register (CAN_IMASK2)............................................................................................... 163240.4.11 Interrupt Masks 1 register (CAN_IMASK1)............................................................................................... 163340.4.12 Interrupt Flags 2 register (CAN_IFLAG2).................................................................................................. 163340.4.13 Interrupt Flags 1 register (CAN_IFLAG1).................................................................................................. 163440.4.14 Control 2 register (CAN_CTRL2)............................................................................................................... 163740.4.15 Error and Status 2 register (CAN_ESR2).................................................................................................... 164140.4.16 CRC Register (CAN_CRCR).......................................................................................................................164240.4.17 Rx FIFO Global Mask register (CAN_RXFGMASK)................................................................................ 164340.4.18 Rx FIFO Information Register (CAN_RXFIR)........................................................................................... 164440.4.19 CAN Bit Timing Register (CAN_CBT)...................................................................................................... 164540.4.20 Rx Individual Mask Registers (CAN_RXIMRn).........................................................................................164740.4.21 Memory Error Control Register (CAN_MECR)......................................................................................... 164840.4.22 Error Injection Address Register (CAN_ERRIAR).....................................................................................165040.4.23 Error Injection Data Pattern Register (CAN_ERRIDPR)............................................................................165240.4.24 Error Injection Parity Pattern Register (CAN_ERRIPPR).......................................................................... 165240.4.25 Error Report Address Register (CAN_RERRAR).......................................................................................165340.4.26 Error Report Data Register (CAN_RERRDR)............................................................................................ 165440.4.27 Error Report Syndrome Register (CAN_RERRSYNR).............................................................................. 165540.4.28 Error Status Register (CAN_ERRSR)......................................................................................................... 165740.4.29 CAN FD Control Register (CAN_FDCTRL).............................................................................................. 165840.4.30 CAN FD Bit Timing Register (CAN_FDCBT)........................................................................................... 166240.4.31 CAN FD CRC Register (CAN_FDCRC).....................................................................................................166440.4.32 Message buffer structure..............................................................................................................................166640.4.33 FlexCAN Memory Partition for CAN FD................................................................................................... 167240.4.34 FlexCAN message buffer memory map.......................................................................................................167340.4.35 Rx FIFO structure........................................................................................................................................ 167840.5 Functional description...................................................................................................................................................168040.5.1 Transmit process.......................................................................................................................................... 1681S32V234 Reference Manual, Rev. 5, 11/201942 NXP SemiconductorsSection number Title Page40.5.2 Arbitration process.......................................................................................................................................168240.5.3 Receive process............................................................................................................................................168640.5.4 Matching process......................................................................................................................................... 168840.5.5 Move process............................................................................................................................................... 169340.5.6 Data coherence.............................................................................................................................................169540.5.7 Rx FIFO....................................................................................................................................................... 169840.5.8 CAN protocol related features..................................................................................................................... 170140.5.9 Clock domains and restrictions.................................................................................................................... 172240.5.10 Modes of operation details...........................................................................................................................172740.5.11 Interrupts...................................................................................................................................................... 172940.5.12 Bus interface................................................................................................................................................ 173140.5.13 Detection and Correction of Memory Errors............................................................................................... 173140.6 Initialization/application information........................................................................................................................... 173640.6.1 FlexCAN initialization sequence................................................................................................................. 1736Chapter 41Inter-Integrated Circuit (I2C)41.1 Chip specific I2C information...................................................................................................................................... 173941.1.1 I2C Instances................................................................................................................................................173941.1.2 I2C Clocking................................................................................................................................................ 173941.2 Overview.......................................................................................................................................................................173941.3 Introduction to I2C........................................................................................................................................................174041.3.1 Definition: I2C module................................................................................................................................ 174041.3.2 Advantages of the I2C bus........................................................................................................................... 174041.3.3 Module block diagram................................................................................................................................. 174041.3.4 Features........................................................................................................................................................ 174141.3.5 Modes of operation...................................................................................................................................... 174241.3.6 Definition: I2C conditions........................................................................................................................... 174341.4 External signal descriptions.......................................................................................................................................... 174441.4.1 Signal overview............................................................................................................................................1744S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 43Section number Title Page41.4.2 Detailed external signal descriptions........................................................................................................... 174441.5 Memory map and register definition.............................................................................................................................174441.5.1 Register accessibility....................................................................................................................................174541.5.2 Register figure conventions......................................................................................................................... 174541.5.3 I2C Bus Address Register (I2C_IBAD).......................................................................................................174641.5.4 I2C Bus Frequency Divider Register (I2C_IBFD)...................................................................................... 174741.5.5 I2C Bus Control Register (I2C_IBCR)........................................................................................................174741.5.6 I2C Bus Status Register (I2C_IBSR)...........................................................................................................174941.5.7 I2C Bus Data I/O Register (I2C_IBDR)...................................................................................................... 175041.5.8 I2C Bus Interrupt Config Register (I2C_IBIC)........................................................................................... 175141.5.9 I2C Bus Debug Register (I2C_IBDBG)...................................................................................................... 175241.6 Functional description...................................................................................................................................................175341.6.1 Notes about module operation..................................................................................................................... 175341.6.2 Transactions................................................................................................................................................. 175441.6.3 Arbitration procedure...................................................................................................................................175841.6.4 Clock behavior............................................................................................................................................. 175841.6.5 Interrupts...................................................................................................................................................... 177241.6.6 STOP mode.................................................................................................................................................. 177341.6.7 DEBUG mode.............................................................................................................................................. 177341.6.8 DMA interface............................................................................................................................................. 177541.7 Initialization/application information........................................................................................................................... 177641.7.1 Recommended interrupt service flow.......................................................................................................... 177641.7.2 General programming guidelines (for both master and slave mode)...........................................................177741.7.3 Programming guidelines specific to master mode....................................................................................... 177941.7.4 Programming guidelines specific to slave mode..........................................................................................178341.7.5 DMA application information......................................................................................................................1783Chapter 42Serial Peripheral Interface (SPI)42.1 Chip-specific SPI information...................................................................................................................................... 1791S32V234 Reference Manual, Rev. 5, 11/201944 NXP SemiconductorsSection number Title Page42.2 SPI Clocking................................................................................................................................................................. 179142.3 Introduction...................................................................................................................................................................179142.3.1 Block Diagram............................................................................................................................................. 179142.3.2 Features........................................................................................................................................................ 179242.3.3 Interface configurations............................................................................................................................... 179442.3.4 Modes of Operation..................................................................................................................................... 179542.4 Module signal descriptions........................................................................................................................................... 179742.4.1 PCS0/SS—Peripheral Chip Select/Slave Select.......................................................................................... 179742.4.2 PCS1–PCS3—Peripheral Chip Selects 1–3.................................................................................................179742.4.3 PCS4—Peripheral Chip Select 4..................................................................................................................179742.4.4 PCS5/PCSS—Peripheral Chip Select 5/Peripheral Chip Select Strobe.......................................................179842.4.5 PCS6–PCS7—Peripheral Chip Selects 6–7.................................................................................................179842.4.6 SCK—Serial Clock...................................................................................................................................... 179842.4.7 SIN—Serial Input........................................................................................................................................ 179842.4.8 SOUT—Serial Output..................................................................................................................................179942.5 Memory Map/Register Definition.................................................................................................................................179942.5.1 Module Configuration Register (SPI_MCR)............................................................................................... 180142.5.2 Transfer Count Register (SPI_TCR)............................................................................................................180542.5.3 Clock and Transfer Attributes Register (In Master Mode) (SPI_CTARn)..................................................180542.5.4 Clock and Transfer Attributes Register (In Slave Mode) (SPI_CTARn_SLAVE)..................................... 181042.5.5 Status Register (SPI_SR)............................................................................................................................. 181242.5.6 DMA/Interrupt Request Select and Enable Register (SPI_RSER)..............................................................181542.5.7 PUSH TX FIFO Register In Master Mode (SPI_PUSHR).......................................................................... 181842.5.8 PUSH TX FIFO Register In Slave Mode (SPI_PUSHR_SLAVE)............................................................. 182042.5.9 POP RX FIFO Register (SPI_POPR).......................................................................................................... 182142.5.10 Transmit FIFO Registers (SPI_TXFRn)...................................................................................................... 182142.5.11 Receive FIFO Registers (SPI_RXFRn)....................................................................................................... 182242.5.12 Clock and Transfer Attributes Register Extended (SPI_CTAREn).............................................................182242.5.13 Status Register Extended (SPI_SREX)........................................................................................................1824S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 45Section number Title Page42.6 Functional description...................................................................................................................................................182542.6.1 Start and Stop of module transfers...............................................................................................................182642.6.2 Serial Peripheral Interface SPI configuration.............................................................................................. 182742.6.3 Module baud rate and clock delay generation............................................................................................. 183242.6.4 Transfer formats...........................................................................................................................................183542.6.5 Continuous Serial Communications Clock.................................................................................................. 184642.6.6 Slave Mode Operation Constraints.............................................................................................................. 184842.6.7 Parity Generation and Check....................................................................................................................... 184842.6.8 Interrupts/DMA requests..............................................................................................................................184942.6.9 Power saving features.................................................................................................................................. 185342.7 Initialization/application information........................................................................................................................... 185442.7.1 How to manage queues................................................................................................................................ 185442.7.2 Switching Master and Slave mode...............................................................................................................185542.7.3 Initializing Module in Master/Slave Modes.................................................................................................185542.7.4 Baud rate settings......................................................................................................................................... 185542.7.5 Delay settings...............................................................................................................................................185642.7.6 Calculation of FIFO pointer addresses.........................................................................................................1857Chapter 4310/100/1000-Mbps Ethernet MAC (ENET)43.1 Chip-specific ENET information..................................................................................................................................186143.2 Programming ENET_MSCR[HOLDTIME].................................................................................................................186243.3 Selecting RMII or RGMII mode...................................................................................................................................186243.4 Recieve Parser Match Array Table Depth.................................................................................................................... 186243.5 Timer Slave mode.........................................................................................................................................................186243.6 Introduction...................................................................................................................................................................186343.7 Overview.......................................................................................................................................................................186343.7.1 Features........................................................................................................................................................ 186343.7.2 Block diagram.............................................................................................................................................. 186643.8 External signal description............................................................................................................................................1867S32V234 Reference Manual, Rev. 5, 11/201946 NXP SemiconductorsSection number Title Page43.9 Memory map/register definition................................................................................................................................... 187043.9.1 Interrupt Event Register (ENET_EIR).........................................................................................................187743.9.2 Interrupt Mask Register (ENET_EIMR)......................................................................................................188143.9.3 Receive Descriptor Active Register - Ring 0 (ENET_RDAR)....................................................................188543.9.4 Transmit Descriptor Active Register - Ring 0 (ENET_TDAR).................................................................. 188543.9.5 Ethernet Control Register (ENET_ECR).....................................................................................................188743.9.6 MII Management Frame Register (ENET_MMFR).................................................................................... 188943.9.7 MII Speed Control Register (ENET_MSCR).............................................................................................. 189043.9.8 MIB Control Register (ENET_MIBC)........................................................................................................ 189243.9.9 Receive Control Register (ENET_RCR)..................................................................................................... 189343.9.10 Transmit Control Register (ENET_TCR).................................................................................................... 189643.9.11 Physical Address Lower Register (ENET_PALR)...................................................................................... 189843.9.12 Physical Address Upper Register (ENET_PAUR)...................................................................................... 189843.9.13 Opcode/Pause Duration Register (ENET_OPD)......................................................................................... 189943.9.14 Transmit Interrupt Coalescing Register (ENET_TXICn)............................................................................189943.9.15 Receive Interrupt Coalescing Register (ENET_RXICn)............................................................................. 190043.9.16 Descriptor Individual Upper Address Register (ENET_IAUR).................................................................. 190143.9.17 Descriptor Individual Lower Address Register (ENET_IALR).................................................................. 190243.9.18 Descriptor Group Upper Address Register (ENET_GAUR).......................................................................190243.9.19 Descriptor Group Lower Address Register (ENET_GALR).......................................................................190343.9.20 Transmit FIFO Watermark Register (ENET_TFWR)................................................................................. 190343.9.21 Receive Descriptor Ring 1 Start Register (ENET_RDSR1)........................................................................190443.9.22 Transmit Buffer Descriptor Ring 1 Start Register (ENET_TDSR1)........................................................... 190543.9.23 Maximum Receive Buffer Size Register - Ring 1 (ENET_MRBR1)..........................................................190643.9.24 Receive Descriptor Ring 2 Start Register (ENET_RDSR2)........................................................................190743.9.25 Transmit Buffer Descriptor Ring 2 Start Register (ENET_TDSR2)........................................................... 190743.9.26 Maximum Receive Buffer Size Register - Ring 2 (ENET_MRBR2)..........................................................190843.9.27 Receive Descriptor Ring 0 Start Register (ENET_RDSR)..........................................................................190943.9.28 Transmit Buffer Descriptor Ring 0 Start Register (ENET_TDSR)............................................................. 1910S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 47Section number Title Page43.9.29 Maximum Receive Buffer Size Register - Ring 0 (ENET_MRBR)............................................................191043.9.30 Receive FIFO Section Full Threshold (ENET_RSFL)................................................................................ 191143.9.31 Receive FIFO Section Empty Threshold (ENET_RSEM).......................................................................... 191243.9.32 Receive FIFO Almost Empty Threshold (ENET_RAEM).......................................................................... 191243.9.33 Receive FIFO Almost Full Threshold (ENET_RAFL)................................................................................191343.9.34 Transmit FIFO Section Empty Threshold (ENET_TSEM)......................................................................... 191343.9.35 Transmit FIFO Almost Empty Threshold (ENET_TAEM).........................................................................191443.9.36 Transmit FIFO Almost Full Threshold (ENET_TAFL).............................................................................. 191443.9.37 Transmit Inter-Packet Gap (ENET_TIPG).................................................................................................. 191543.9.38 Frame Truncation Length (ENET_FTRL)...................................................................................................191543.9.39 Transmit Accelerator Function Configuration (ENET_TACC).................................................................. 191643.9.40 Receive Accelerator Function Configuration (ENET_RACC)....................................................................191743.9.41 Receive Classification Match Register for Class n (ENET_RCMRn)........................................................ 191843.9.42 DMA Class Based Configuration (ENET_DMAnCFG)............................................................................. 191943.9.43 Receive Descriptor Active Register - Ring 1 (ENET_RDAR1)..................................................................192143.9.44 Transmit Descriptor Active Register - Ring 1 (ENET_TDAR1)................................................................ 192243.9.45 Receive Descriptor Active Register - Ring 2 (ENET_RDAR2)..................................................................192343.9.46 Transmit Descriptor Active Register - Ring 2 (ENET_TDAR2)................................................................ 192443.9.47 QOS Scheme (ENET_QOS)........................................................................................................................ 192443.9.48 Reserved Statistic Register (ENET_RMON_T_DROP)..............................................................................192643.9.49 Tx Packet Count Statistic Register (ENET_RMON_T_PACKETS).......................................................... 192643.9.50 Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)......................................................192743.9.51 Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)......................................................192743.9.52 Tx Packets with CRC/Align Error Statistic Register (ENET_RMON_T_CRC_ALIGN).......................... 192843.9.53 Tx Packets Less Than Bytes and Good CRC Statistic Register (ENET_RMON_T_UNDERSIZE)..........192843.9.54 Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (ENET_RMON_T_OVERSIZE)........192843.9.55 Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_T_FRAG)...................192943.9.56 Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (ENET_RMON_T_JAB)...... 192943.9.57 Tx Collision Count Statistic Register (ENET_RMON_T_COL)................................................................ 1930S32V234 Reference Manual, Rev. 5, 11/201948 NXP SemiconductorsSection number Title Page43.9.58 Tx 64-Byte Packets Statistic Register (ENET_RMON_T_P64)................................................................. 193043.9.59 Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127).......................................... 193043.9.60 Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)...................................... 193143.9.61 Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)...................................... 193143.9.62 Tx 512- to 1023-byte Packets Statistic Register (ENET_RMON_T_P512TO1023).................................. 193243.9.63 Tx 1024- to 2047-byte Packets Statistic Register (ENET_RMON_T_P1024TO2047).............................. 193243.9.64 Tx Packets Greater Than 2048 Bytes Statistic Register (ENET_RMON_T_P_GTE2048)........................ 193343.9.65 Tx Octets Statistic Register (ENET_RMON_T_OCTETS)........................................................................ 193343.9.66 Reserved Statistic Register (ENET_IEEE_T_DROP).................................................................................193343.9.67 Frames Transmitted OK Statistic Register (ENET_IEEE_T_FRAME_OK).............................................. 193443.9.68 Frames Transmitted with Single Collision Statistic Register (ENET_IEEE_T_1COL)............................. 193443.9.69 Frames Transmitted with Multiple Collisions Statistic Register (ENET_IEEE_T_MCOL).......................193543.9.70 Frames Transmitted after Deferral Delay Statistic Register (ENET_IEEE_T_DEF)..................................193543.9.71 Frames Transmitted with Late Collision Statistic Register (ENET_IEEE_T_LCOL)................................ 193543.9.72 Frames Transmitted with Excessive Collisions Statistic Register (ENET_IEEE_T_EXCOL)...................193643.9.73 Frames Transmitted with Tx FIFO Underrun Statistic Register (ENET_IEEE_T_MACERR)..................193643.9.74 Frames Transmitted with Carrier Sense Error Statistic Register (ENET_IEEE_T_CSERR)..................... 193743.9.75 Reserved Statistic Register (ENET_IEEE_T_SQE).................................................................................... 193743.9.76 Flow Control Pause Frames Transmitted Statistic Register (ENET_IEEE_T_FDXFC).............................193743.9.77 Octet Count for Frames Transmitted w/o Error Statistic Register (ENET_IEEE_T_OCTETS_OK).........193843.9.78 Rx Packet Count Statistic Register (ENET_RMON_R_PACKETS).......................................................... 193843.9.79 Rx Broadcast Packets Statistic Register (ENET_RMON_R_BC_PKT)..................................................... 193943.9.80 Rx Multicast Packets Statistic Register (ENET_RMON_R_MC_PKT)..................................................... 193943.9.81 Rx Packets with CRC/Align Error Statistic Register (ENET_RMON_R_CRC_ALIGN)..........................193943.9.82 Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register(ENET_RMON_R_UNDERSIZE)..............................................................................................................194043.9.83 Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (ENET_RMON_R_OVERSIZE).194043.9.84 Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_R_FRAG).................. 194143.9.85 Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (ENET_RMON_R_JAB)..... 1941S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 49Section number Title Page43.9.86 Reserved Statistic Register (ENET_RMON_R_RESVD_0).......................................................................194143.9.87 Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64).................................................................194243.9.88 Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127)......................................... 194243.9.89 Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255)..................................... 194343.9.90 Rx 256- to 511-Byte Packets Statistic Register (ENET_RMON_R_P256TO511)..................................... 194343.9.91 Rx 512- to 1023-Byte Packets Statistic Register (ENET_RMON_R_P512TO1023)................................. 194343.9.92 Rx 1024- to 2047-Byte Packets Statistic Register (ENET_RMON_R_P1024TO2047)............................. 194443.9.93 Rx Packets Greater than 2048 Bytes Statistic Register (ENET_RMON_R_P_GTE2048)......................... 194443.9.94 Rx Octets Statistic Register (ENET_RMON_R_OCTETS)........................................................................194543.9.95 Frames not Counted Correctly Statistic Register (ENET_IEEE_R_DROP)............................................... 194543.9.96 Frames Received OK Statistic Register (ENET_IEEE_R_FRAME_OK).................................................. 194543.9.97 Frames Received with CRC Error Statistic Register (ENET_IEEE_R_CRC)............................................ 194643.9.98 Frames Received with Alignment Error Statistic Register (ENET_IEEE_R_ALIGN).............................. 194643.9.99 Receive FIFO Overflow Count Statistic Register (ENET_IEEE_R_MACERR)........................................194743.9.100 Flow Control Pause Frames Received Statistic Register (ENET_IEEE_R_FDXFC).................................194743.9.101 Octet Count for Frames Received without Error Statistic Register (ENET_IEEE_R_OCTETS_OK).......194743.9.102 Adjustable Timer Control Register (ENET_ATCR)................................................................................... 194843.9.103 Timer Value Register (ENET_ATVR)........................................................................................................ 195043.9.104 Timer Offset Register (ENET_ATOFF)...................................................................................................... 195043.9.105 Timer Period Register (ENET_ATPER)......................................................................................................195143.9.106 Timer Correction Register (ENET_ATCOR).............................................................................................. 195143.9.107 Time-Stamping Clock Period Register (ENET_ATINC)............................................................................ 195243.9.108 Timestamp of Last Transmitted Frame (ENET_ATSTMP)........................................................................ 195243.9.109 Pattern Match Data Register (ENET_MDATA)..........................................................................................195343.9.110 Match Entry Mask Register (ENET_MMASK).......................................................................................... 195343.9.111 Match Entry Rules Configuration Register (ENET_MCONFIG)............................................................... 195443.9.112 Match Entry Read/Write Command Register (ENET_MENTRYRW).......................................................195543.9.113 Receive Parser Control Register (ENET_RXPCTL)................................................................................... 195643.9.114 Maximum Frame Offset (ENET_MAXFRMOFF)......................................................................................1957S32V234 Reference Manual, Rev. 5, 11/201950 NXP SemiconductorsSection number Title Page43.9.115 Receive Parser Status (ENET_RXPARST)................................................................................................. 195843.9.116 Parser Discard Count (ENET_PARSDSCD)...............................................................................................195943.9.117 Parser Accept Count 0 (ENET_PRSACPT0).............................................................................................. 196043.9.118 Parser Reject Count 0 (ENET_PRSRJCT0)................................................................................................ 196043.9.119 Parser Accept Count 1 (ENET_PRSACPT1).............................................................................................. 196143.9.120 Parser Reject Count 1 (ENET_PRSRJCT1)................................................................................................ 196143.9.121 Parser Accept Count 2 (ENET_PRSACPT2).............................................................................................. 196243.9.122 Parser Reject Count 2 (ENET_PRSRJCT2)................................................................................................ 196243.9.123 Timer Global Status Register (ENET_TGSR).............................................................................................196343.9.124 Timer Control Status Register (ENET_TCSRn)..........................................................................................196443.9.125 Timer Compare Capture Register (ENET_TCCRn)....................................................................................196543.10 Functional description...................................................................................................................................................196643.10.1 Ethernet MAC frame formats...................................................................................................................... 196643.10.2 IP and higher layers frame format................................................................................................................196943.10.3 IEEE 1588 message formats........................................................................................................................ 197343.10.4 MAC receive................................................................................................................................................ 197743.10.5 MAC transmit.............................................................................................................................................. 198643.10.6 Full-duplex flow control operation.............................................................................................................. 199243.10.7 Magic packet detection................................................................................................................................ 199443.10.8 IP accelerator functions................................................................................................................................199543.10.9 Resets and stop controls...............................................................................................................................199943.10.10 IEEE 1588 functions.................................................................................................................................... 200243.10.11 FIFO thresholds............................................................................................................................................200643.10.12 Loopback options.........................................................................................................................................200943.10.13 Legacy buffer descriptors.............................................................................................................................201043.10.14 Enhanced buffer descriptors.........................................................................................................................201143.10.15 Client FIFO application interface................................................................................................................ 201843.10.16 FIFO protection............................................................................................................................................202143.10.17 Reference clock............................................................................................................................................2023S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 51Section number Title Page43.10.18 PHY management interface......................................................................................................................... 202343.10.19 Ethernet interfaces........................................................................................................................................202643.10.20 AVB configuration.......................................................................................................................................203143.10.21 Interrupt coalescence....................................................................................................................................2032Chapter 44ZIPWIRE44.1 Chip-specific Zipwire Information............................................................................................................................... 203544.2 Overview.......................................................................................................................................................................203644.3 Introduction...................................................................................................................................................................203644.4 Zipwire Block Diagram................................................................................................................................................ 203644.5 Architecture...................................................................................................................................................................203744.6 Zipwire interconnections.............................................................................................................................................. 203844.7 Zipwire performance.....................................................................................................................................................203944.7.1 Read performance........................................................................................................................................ 204044.7.2 Write performance....................................................................................................................................... 2043Chapter 45LFAST45.1 LFAST Chip-specific information................................................................................................................................204745.2 Introduction...................................................................................................................................................................204745.3 Block diagram ..............................................................................................................................................................204745.4 External signals.............................................................................................................................................................204845.4.1 LFAST operating data rates......................................................................................................................... 204845.5 LFAST frame structure.................................................................................................................................................204945.6 Features.........................................................................................................................................................................205245.7 Memory map and register definition.............................................................................................................................205345.7.1 LFAST Mode Configuration Register (LFAST_MCR)...............................................................................205545.7.2 LFAST Speed Control Register (LFAST_SCR)..........................................................................................205745.7.3 LFAST Correlator Control Register (LFAST_COCR)................................................................................205845.7.4 LFAST Test Mode Control Register (LFAST_TMCR).............................................................................. 2060S32V234 Reference Manual, Rev. 5, 11/201952 NXP SemiconductorsSection number Title Page45.7.5 LFAST Auto Loopback Control Register (LFAST_ALCR)....................................................................... 206145.7.6 LFAST Rate Change Delay Control Register (LFAST_RCDCR).............................................................. 206245.7.7 LFAST Wakeup Delay Control Register (LFAST_SLCR)......................................................................... 206245.7.8 LFAST ICLC Control Register (LFAST_ICR)........................................................................................... 206445.7.9 LFAST Ping Control Register (LFAST_PICR)...........................................................................................206545.7.10 LFAST Rx FIFO CTS Control Register (LFAST_RFCR).......................................................................... 206645.7.11 LFAST Tx Interrupt Enable Register (LFAST_TIER)................................................................................206645.7.12 LFAST Rx Interrupt Enable Register (LFAST_RIER)............................................................................... 206745.7.13 LFAST Rx ICLC Interrupt Enable Register (LFAST_RIIER)....................................................................206945.7.14 LFAST PLL Control Register (LFAST_PLLCR)....................................................................................... 207145.7.15 LFAST LVDS Control Register (LFAST_LCR).........................................................................................207345.7.16 LFAST Unsolicited Tx Control Register (LFAST_UNSTCR)................................................................... 207545.7.17 LFAST Unsolicited Tx Data Registers (LFAST_UNSTDRn).................................................................... 207645.7.18 LFAST Global Status Register (LFAST_GSR)...........................................................................................207745.7.19 LFAST Ping Status Register (LFAST_PISR)..............................................................................................207845.7.20 LFAST Data Frame Status Register (LFAST_DFSR).................................................................................207945.7.21 LFAST Tx Interrupt Status Register (LFAST_TISR)................................................................................. 208045.7.22 LFAST Rx Interrupt Status Register (LFAST_RISR).................................................................................208145.7.23 LFAST Rx ICLC Interrupt Status Register (LFAST_RIISR)..................................................................... 208345.7.24 LFAST PLL and LVDS Status Register (LFAST_PLLLSR)......................................................................208545.7.25 LFAST Unsolicited Rx Status Register (LFAST_UNSRSR)......................................................................208645.7.26 LFAST Unsolicited Rx Data Register (LFAST_UNSRDRn)..................................................................... 208745.8 Functional description...................................................................................................................................................208745.8.1 Startup procedure......................................................................................................................................... 208745.8.2 Line Receiver............................................................................................................................................... 209045.8.3 Transmit Controller......................................................................................................................................209945.8.4 CTS mode support....................................................................................................................................... 210445.8.5 Frames supported......................................................................................................................................... 210545.8.6 Frame flow................................................................................................................................................... 2106S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 53Section number Title Page45.8.7 Test and Debug Support...............................................................................................................................211345.8.8 Interrupts...................................................................................................................................................... 212245.9 Packet memory..............................................................................................................................................................212545.10 Resets............................................................................................................................................................................ 212645.11 Clocks........................................................................................................................................................................... 212745.11.1 Clocking strategy......................................................................................................................................... 212745.11.2 Slow speed clock..........................................................................................................................................212845.11.3 Rx Controller Clocks................................................................................................................................... 213145.11.4 Clocking Module Requirements for High Speed Phases............................................................................. 213145.11.5 Clock module requirements for low speed phases.......................................................................................213245.11.6 Tx Controller Clocks....................................................................................................................................213345.12 PLL configuration example.......................................................................................................................................... 2134Chapter 46Serial Interprocessor Interface (SIPI)46.1 Serial Interprocessor Interface (SIPI) Device ID..........................................................................................................213546.2 Introduction...................................................................................................................................................................213546.2.1 Scalability.....................................................................................................................................................213546.3 Overview.......................................................................................................................................................................213646.4 SIPI block diagram....................................................................................................................................................... 213846.5 Feature description........................................................................................................................................................213846.5.1 Main features................................................................................................................................................213846.5.2 Standard features..........................................................................................................................................213946.6 SIPI operation from reset..............................................................................................................................................213946.7 Functional description...................................................................................................................................................213946.7.1 External signals............................................................................................................................................ 213946.7.2 Frame format................................................................................................................................................214046.8 Transfer types................................................................................................................................................................214646.8.1 Read transfer................................................................................................................................................ 214646.8.2 Register read answer transfer.......................................................................................................................2147S32V234 Reference Manual, Rev. 5, 11/201954 NXP SemiconductorsSection number Title Page46.8.3 Register Write transfer................................................................................................................................. 214846.8.4 Write Acknowledge transfer........................................................................................................................ 215146.8.5 ID request response......................................................................................................................................215146.9 Transfer API and flow charts........................................................................................................................................215346.10 DMA programming sequence.......................................................................................................................................216046.11 Modes of operation....................................................................................................................................................... 216146.11.1 Initialization mode....................................................................................................................................... 216146.11.2 Normal mode................................................................................................................................................216146.11.3 Module Disable (MD)..................................................................................................................................216146.12 Errors.............................................................................................................................................................................216246.12.1 Timeout error............................................................................................................................................... 216246.12.2 CRC error.....................................................................................................................................................216246.12.3 Maximum count reached error.....................................................................................................................216346.12.4 Transaction ID error.....................................................................................................................................216346.12.5 Acknowledge error.......................................................................................................................................216346.13 CRC calculation............................................................................................................................................................216346.14 Interrupt logic................................................................................................................................................................216446.15 SIPI control and status overview.................................................................................................................................. 216546.16 Memory map and register definition.............................................................................................................................216646.16.1 SIPI Channel Control Register 0 (SIPI_CCR0)...........................................................................................216946.16.2 SIPI Channel Status Register 0 (SIPI_CSR0)..............................................................................................217246.16.3 SIPI Channel Interrupt Register 0 (SIPI_CIR0).......................................................................................... 217346.16.4 SIPI Channel Timeout Register 0 (SIPI_CTOR0).......................................................................................217446.16.5 SIPI Channel CRC Register 0 (SIPI_CCRC0)............................................................................................ 217546.16.6 SIPI Channel Address Register 0 (SIPI_CAR0)..........................................................................................217546.16.7 SIPI Channel Data Register 0 (SIPI_CDR0)............................................................................................... 217646.16.8 SIPI Channel Control Register 1 (SIPI_CCR1)...........................................................................................217646.16.9 SIPI Channel Status Register 1 (SIPI_CSR1)..............................................................................................217946.16.10 SIPI Channel Interrupt Register 1 (SIPI_CIR1).......................................................................................... 2181S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 55Section number Title Page46.16.11 SIPI Channel Timeout Register 1 (SIPI_CTOR1).......................................................................................218246.16.12 SIPI Channel CRC Register 1 (SIPI_CCRC1)............................................................................................ 218346.16.13 SIPI Channel Address Register 1 (SIPI_CAR1)..........................................................................................218346.16.14 SIPI Channel Data Register 1 (SIPI_CDR1)............................................................................................... 218446.16.15 SIPI Channel Control Register 2 (SIPI_CCR2)...........................................................................................218446.16.16 SIPI Channel Status Register 2 (SIPI_CSR2)..............................................................................................218746.16.17 SIPI Channel Interrupt Register 2 (SIPI_CIR2).......................................................................................... 218946.16.18 SIPI Channel Timeout Register 2 (SIPI_CTOR2).......................................................................................219046.16.19 SIPI Channel CRC Register 2 (SIPI_CCRC2)............................................................................................ 219146.16.20 SIPI Channel Address Register 2 (SIPI_CAR2)..........................................................................................219146.16.21 SIPI Channel Data Register 2 (SIPI_CDR2_n)........................................................................................... 219246.16.22 SIPI Channel Control Register 3 (SIPI_CCR3)...........................................................................................219246.16.23 SIPI Channel Status Register 3 (SIPI_CSR3)..............................................................................................219546.16.24 SIPI Channel Interrupt Register 3 (SIPI_CIR3).......................................................................................... 219746.16.25 SIPI Channel Timeout Register 3 (SIPI_CTOR3).......................................................................................219846.16.26 SIPI Channel CRC Register 3 (SIPI_CCRC3)............................................................................................ 219946.16.27 SIPI Channel Address Register 3 (SIPI_CAR3)..........................................................................................219946.16.28 SIPI Channel Data Register 3 (SIPI_CDR3)............................................................................................... 220046.16.29 SIPI Module Configuration Register (SIPI_MCR)......................................................................................220046.16.30 SIPI Status Register (SIPI_SR)....................................................................................................................220346.16.31 SIPI Max Count Register (SIPI_MAXCR)..................................................................................................220546.16.32 SIPI Address Reload Register (SIPI_ARR).................................................................................................220546.16.33 SIPI Address Count Register (SIPI_ACR).................................................................................................. 220646.16.34 SIPI Error Register (SIPI_ERR).................................................................................................................. 2207Chapter 47LINFlexD47.1 Chip specific LinFlexD information.............................................................................................................................221147.1.1 LinFlexD Configurations............................................................................................................................. 221147.1.2 LIN_CLK and BUS clock relationship........................................................................................................2211S32V234 Reference Manual, Rev. 5, 11/201956 NXP SemiconductorsSection number Title Page47.2 Introduction...................................................................................................................................................................221247.2.1 Glossary and acronyms................................................................................................................................ 221247.2.2 References....................................................................................................................................................221247.3 Main features................................................................................................................................................................ 221447.3.1 LIN mode features....................................................................................................................................... 221447.3.2 UART mode features................................................................................................................................... 221547.4 Functional description...................................................................................................................................................221547.4.1 LIN protocol.................................................................................................................................................221547.4.2 LINFlexD features....................................................................................................................................... 221847.4.3 Timer............................................................................................................................................................223447.4.4 UART mode.................................................................................................................................................223547.4.5 DMA interface............................................................................................................................................. 223947.5 Memory map and register description.......................................................................................................................... 225847.5.1 LIN Control Register 1 (LINFlexD_LINCR1)............................................................................................ 226047.5.2 LIN Interrupt enable register (LINFlexD_LINIER).................................................................................... 226347.5.3 LIN Status Register (LINFlexD_LINSR).................................................................................................... 226547.5.4 LIN Error Status Register (LINFlexD_LINESR)........................................................................................ 226847.5.5 UART Mode Control Register (LINFlexD_UARTCR).............................................................................. 227047.5.6 UART Mode Status Register (LINFlexD_UARTSR)................................................................................. 227547.5.7 LIN Time-Out Control Status Register (LINFlexD_LINTCSR).................................................................227747.5.8 LIN Output Compare Register (LINFlexD_LINOCR)................................................................................227947.5.9 LIN Time-Out Control Register (LINFlexD_LINTOCR)........................................................................... 228047.5.10 LIN Fractional Baud Rate Register (LINFlexD_LINFBRR)...................................................................... 228047.5.11 LIN Integer Baud Rate Register (LINFlexD_LINIBRR)............................................................................ 228147.5.12 LIN Checksum Field Register (LINFlexD_LINCFR)................................................................................. 228247.5.13 LIN Control Register 2 (LINFlexD_LINCR2)............................................................................................ 228347.5.14 Buffer Identifier Register (LINFlexD_BIDR)............................................................................................. 228547.5.15 Buffer Data Register Least Significant (LINFlexD_BDRL)....................................................................... 228647.5.16 Buffer Data Register Most Significant (LINFlexD_BDRM)...................................................................... 2287S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 57Section number Title Page47.5.17 Identifier Filter Enable Register (LINFlexD_IFER)....................................................................................228747.5.18 Identifier Filter Match Index (LINFlexD_IFMI)......................................................................................... 228847.5.19 Identifier Filter Mode Register (LINFlexD_IFMR).................................................................................... 228847.5.20 Identifier Filter Control Register (LINFlexD_IFCRn)................................................................................ 228947.5.21 Global Control Register (LINFlexD_GCR).................................................................................................229047.5.22 UART Preset Timeout Register (LINFlexD_UARTPTO).......................................................................... 229247.5.23 UART Current Timeout Register (LINFlexD_UARTCTO)....................................................................... 229347.5.24 DMA Tx Enable Register (LINFlexD_DMATXE)..................................................................................... 229447.5.25 DMA Rx Enable Register (LINFlexD_DMARXE).....................................................................................229447.6 Programming considerations........................................................................................................................................ 229547.6.1 Master node..................................................................................................................................................229547.6.2 Slave node.................................................................................................................................................... 229747.6.3 Timeout........................................................................................................................................................ 230247.6.4 UART mode.................................................................................................................................................230347.6.5 Interrupts...................................................................................................................................................... 230447.6.6 LINFlexD Clock Tolerance......................................................................................................................... 2305Chapter 48FlexRay Communication Controller (FlexRay)48.1 Introduction...................................................................................................................................................................230748.1.1 Reference..................................................................................................................................................... 230748.1.2 Glossary....................................................................................................................................................... 230748.1.3 Overview......................................................................................................................................................230948.1.4 Features........................................................................................................................................................ 231048.1.5 Modes of operation...................................................................................................................................... 231248.2 External Signal Description.......................................................................................................................................... 231348.2.1 Detailed Signal Descriptions........................................................................................................................231448.3 Controller Host Interface Clocking...............................................................................................................................231548.4 Protocol Engine Clocking.............................................................................................................................................231548.4.1 Oscillator Clocking...................................................................................................................................... 2316S32V234 Reference Manual, Rev. 5, 11/201958 NXP SemiconductorsSection number Title Page48.4.2 PLL Clocking...............................................................................................................................................231648.5 Register Descriptions....................................................................................................................................................231648.5.1 Register Reset.............................................................................................................................................. 231748.5.2 Register Write Access..................................................................................................................................231748.6 Memory map and register definition.............................................................................................................................231948.6.1 Module Version Register (FR_MVR)..........................................................................................................235548.6.2 Module Configuration Register (FR_MCR)................................................................................................ 235548.6.3 System Memory Base Address High Register (FR_SYMBADHR)............................................................235848.6.4 System Memory Base Address Low Register (FR_SYMBADLR).............................................................235948.6.5 Strobe Signal Control Register (FR_STBSCR)........................................................................................... 235948.6.6 Message Buffer Data Size Register (FR_MBDSR).....................................................................................236148.6.7 Message Buffer Segment Size and Utilization Register (FR_MBSSUTR).................................................236248.6.8 PE DRAM Access Register (FR_PEDRAR)............................................................................................... 236348.6.9 PE DRAM Data Register (FR_PEDRDR)...................................................................................................236448.6.10 Protocol Operation Control Register (FR_POCR).......................................................................................236448.6.11 Global Interrupt Flag and Enable Register (FR_GIFER)............................................................................ 236648.6.12 Protocol Interrupt Flag Register 0 (FR_PIFR0)...........................................................................................236948.6.13 Protocol Interrupt Flag Register 1 (FR_PIFR1)...........................................................................................237148.6.14 Protocol Interrupt Enable Register 0 (FR_PIER0)...................................................................................... 237348.6.15 Protocol Interrupt Enable Register 1 (FR_PIER1)...................................................................................... 237548.6.16 CHI Error Flag Register (FR_CHIERFR)................................................................................................... 237648.6.17 Message Buffer Interrupt Vector Register (FR_MBIVEC).........................................................................237948.6.18 Channel A Status Error Counter Register (FR_CASERCR)....................................................................... 238048.6.19 Channel B Status Error Counter Register (FR_CBSERCR)........................................................................238048.6.20 Protocol Status Register 0 (FR_PSR0)........................................................................................................ 238148.6.21 Protocol Status Register 1 (FR_PSR1)........................................................................................................ 238348.6.22 Protocol Status Register 2 (FR_PSR2)........................................................................................................ 238448.6.23 Protocol Status Register 3 (FR_PSR3)........................................................................................................ 238648.6.24 Macrotick Counter Register (FR_MTCTR).................................................................................................2388S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 59Section number Title Page48.6.25 Cycle Counter Register (FR_CYCTR)........................................................................................................ 238948.6.26 Slot Counter Channel A Register (FR_SLTCTAR).................................................................................... 238948.6.27 Slot Counter Channel B Register (FR_SLTCTBR).....................................................................................239048.6.28 Rate Correction Value Register (FR_RTCORVR)......................................................................................239048.6.29 Offset Correction Value Register (FR_OFCORVR)................................................................................... 239148.6.30 Combined Interrupt Flag Register (FR_CIFR)............................................................................................ 239248.6.31 System Memory Access Time-Out Register (FR_SYMATOR)..................................................................239348.6.32 Sync Frame Counter Register (FR_SFCNTR).............................................................................................239448.6.33 Sync Frame Table Offset Register (FR_SFTOR)........................................................................................ 239448.6.34 Sync Frame Table Configuration, Control, Status Register (FR_SFTCCSR).............................................239548.6.35 Sync Frame ID Rejection Filter Register (FR_SFIDRFR).......................................................................... 239748.6.36 Sync Frame ID Acceptance Filter Value Register (FR_SFIDAFVR)......................................................... 239748.6.37 Sync Frame ID Acceptance Filter Mask Register (FR_SFIDAFMR)......................................................... 239848.6.38 Network Management Vector Register (FR_NMVRn)............................................................................... 239848.6.39 Network Management Vector Length Register (FR_NMVLR).................................................................. 239948.6.40 Timer Configuration and Control Register (FR_TICCR)............................................................................239948.6.41 Timer 1 Cycle Set Register (FR_TI1CYSR)............................................................................................... 240148.6.42 Timer 1 Macrotick Offset Register (FR_TI1MTOR).................................................................................. 240248.6.43 Timer 2 Configuration Register 0 (Absolute Timer Configuration) (FR_TI2CR0_ABS).......................... 240248.6.44 Timer 2 Configuration Register 0 (Relative Timer Configuration) (FR_TI2CR0_REL)............................240348.6.45 Timer 2 Configuration Register 1 (Absolute Timer Configuration) (FR_TI2CR1_ABS).......................... 240348.6.46 Timer 2 Configuration Register 1 (Relative Timer Configuration) (FR_TI2CR1_REL)............................240448.6.47 Slot Status Selection Register (FR_SSSR).................................................................................................. 240548.6.48 Slot Status Counter Condition Register (FR_SSCCR)................................................................................ 240648.6.49 Slot Status Register (FR_SSRn).................................................................................................................. 240848.6.50 Slot Status Counter Register (FR_SSCRn)..................................................................................................241048.6.51 MTS A Configuration Register (FR_MTSACFR).......................................................................................241048.6.52 MTS B Configuration Register (FR_MTSBCFR)....................................................................................... 241148.6.53 Receive Shadow Buffer Index Register (FR_RSBIR).................................................................................2412S32V234 Reference Manual, Rev. 5, 11/201960 NXP SemiconductorsSection number Title Page48.6.54 Receive FIFO Watermark and Selection Register (FR_RFWMSR)........................................................... 241348.6.55 Receive FIFO Start Index Register (FR_RFSIR)........................................................................................ 241448.6.56 Receive FIFO Depth and Size Register (FR_RFDSR)................................................................................ 241448.6.57 Receive FIFO A Read Index Register (FR_RFARIR).................................................................................241548.6.58 Receive FIFO B Read Index Register (FR_RFBRIR)................................................................................. 241548.6.59 Receive FIFO Message ID Acceptance Filter Value Register (FR_RFMIDAFVR)...................................241648.6.60 Receive FIFO Message ID Acceptance Filter Mask Register (FR_RFMIDAFMR)...................................241648.6.61 Receive FIFO Frame ID Rejection Filter Value Register (FR_RFFIDRFVR)........................................... 241748.6.62 Receive FIFO Frame ID Rejection Filter Mask Register (FR_RFFIDRFMR)........................................... 241748.6.63 Receive FIFO Range Filter Configuration Register (FR_RFRFCFR).........................................................241848.6.64 Receive FIFO Range Filter Control Register (FR_RFRFCTR)...................................................................241948.6.65 Last Dynamic Transmit Slot Channel A Register (FR_LDTXSLAR)........................................................ 242048.6.66 Last Dynamic Transmit Slot Channel B Register (FR_LDTXSLBR).........................................................242148.6.67 Protocol Configuration Register 0 (FR_PCR0)........................................................................................... 242148.6.68 Protocol Configuration Register 1 (FR_PCR1)........................................................................................... 242448.6.69 Protocol Configuration Register 2 (FR_PCR2)........................................................................................... 242448.6.70 Protocol Configuration Register 3 (FR_PCR3)........................................................................................... 242548.6.71 Protocol Configuration Register 4 (FR_PCR4)........................................................................................... 242548.6.72 Protocol Configuration Register 5 (FR_PCR5)........................................................................................... 242648.6.73 Protocol Configuration Register 6 (FR_PCR6)........................................................................................... 242648.6.74 Protocol Configuration Register 7 (FR_PCR7)........................................................................................... 242748.6.75 Protocol Configuration Register 8 (FR_PCR8)........................................................................................... 242748.6.76 Protocol Configuration Register 9 (FR_PCR9)........................................................................................... 242848.6.77 Protocol Configuration Register 10 (FR_PCR10)....................................................................................... 242948.6.78 Protocol Configuration Register 11 (FR_PCR11)....................................................................................... 242948.6.79 Protocol Configuration Register 12 (FR_PCR12)....................................................................................... 243048.6.80 Protocol Configuration Register 13 (FR_PCR13)....................................................................................... 243048.6.81 Protocol Configuration Register 14 (FR_PCR14)....................................................................................... 243148.6.82 Protocol Configuration Register 15 (FR_PCR15)....................................................................................... 2431S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 61Section number Title Page48.6.83 Protocol Configuration Register 16 (FR_PCR16)....................................................................................... 243248.6.84 Protocol Configuration Register 17 (FR_PCR17)....................................................................................... 243248.6.85 Protocol Configuration Register 18 (FR_PCR18)....................................................................................... 243348.6.86 Protocol Configuration Register 19 (FR_PCR19)....................................................................................... 243348.6.87 Protocol Configuration Register 20 (FR_PCR20)....................................................................................... 243448.6.88 Protocol Configuration Register 21 (FR_PCR21)....................................................................................... 243448.6.89 Protocol Configuration Register 22 (FR_PCR22)....................................................................................... 243548.6.90 Protocol Configuration Register 23 (FR_PCR23)....................................................................................... 243548.6.91 Protocol Configuration Register 24 (FR_PCR24)....................................................................................... 243648.6.92 Protocol Configuration Register 25 (FR_PCR25)....................................................................................... 243648.6.93 Protocol Configuration Register 26 (FR_PCR26)....................................................................................... 243748.6.94 Protocol Configuration Register 27 (FR_PCR27)....................................................................................... 243748.6.95 Protocol Configuration Register 28 (FR_PCR28)....................................................................................... 243848.6.96 Protocol Configuration Register 29 (FR_PCR29)....................................................................................... 243848.6.97 Protocol Configuration Register 30 (FR_PCR30)....................................................................................... 243948.6.98 StopWatch Count High Register (FR_STPWHR)....................................................................................... 244048.6.99 Stop Watch Count Low Register (FR_STPWLR)....................................................................................... 244048.6.100 Protocol Event Output Enable and StopWatch Control Register (FR_PEOER)......................................... 244048.6.101 Receive FIFO Start Data Offset Register (FR_RFSDOR)...........................................................................244148.6.102 Receive FIFO System Memory Base Address High Register (FR_RFSYMBADHR)............................... 244248.6.103 Receive FIFO System Memory Base Address Low Register (FR_RFSYMBADLR)................................ 244248.6.104 Receive FIFO Periodic Timer Register (FR_RFPTR).................................................................................244348.6.105 Receive FIFO Fill Level and POP Count Register (FR_RFFLPCR)...........................................................244448.6.106 ECC Error Interrupt Flag and Enable Register (FR_EEIFER).................................................................... 244548.6.107 ECC Error Report and Injection Control Register (FR_EERICR).............................................................. 244748.6.108 ECC Error Report Address Register (FR_EERAR).................................................................................... 244848.6.109 ECC Error Report Data Register (FR_EERDR).......................................................................................... 244948.6.110 ECC Error Report Code Register (FR_EERCR)......................................................................................... 245048.6.111 ECC Error Injection Address Register (FR_EEIAR).................................................................................. 2451S32V234 Reference Manual, Rev. 5, 11/201962 NXP SemiconductorsSection number Title Page48.6.112 ECC Error Injection Data Register (FR_EEIDR)........................................................................................ 245148.6.113 ECC Error Injection Code Register (FR_EEICR)....................................................................................... 245248.6.114 Message Buffer Configuration, Control, Status Register (FR_MBCCSRn)............................................... 245248.6.115 Message Buffer Cycle Counter Filter Register (FR_MBCCFRn)............................................................... 245448.6.116 Message Buffer Frame ID Register (FR_MBFIDRn)..................................................................................245648.6.117 Message Buffer Index Register (FR_MBIDXRn)....................................................................................... 245648.6.118 Message Buffer Data Field Offset Register (FR_MBDORn)......................................................................245748.6.119 LRAM ECC Error Test Register (FR_LEETRn).........................................................................................245848.7 Functional Description..................................................................................................................................................245848.7.1 Message Buffer Concept..............................................................................................................................245848.7.2 Physical Message Buffer..............................................................................................................................245848.7.3 Message Buffer Types................................................................................................................................. 246048.7.4 FlexRay Memory Area Layout.................................................................................................................... 246948.7.5 Physical Message Buffer Description.......................................................................................................... 247348.7.6 Individual Message Buffer Functional Description..................................................................................... 248448.7.7 Individual Message Buffer Search...............................................................................................................250448.7.8 Individual Message Buffer Reconfiguration................................................................................................250848.7.9 Receive FIFOs..............................................................................................................................................250848.7.10 Channel Device Modes................................................................................................................................ 251748.7.11 External Clock Synchronization.................................................................................................................. 251948.7.12 Sync Frame ID and Sync Frame Deviation Tables......................................................................................252048.7.13 MTS Generation...........................................................................................................................................252448.7.14 Key Slot Transmission................................................................................................................................. 252448.7.15 Sync Frame Filtering....................................................................................................................................252548.7.16 Strobe Signal Support.................................................................................................................................. 252748.7.17 Timer Support.............................................................................................................................................. 252848.7.18 Slot Status Monitoring................................................................................................................................. 253048.7.19 System Bus Access...................................................................................................................................... 253448.7.20 Interrupt Support.......................................................................................................................................... 2536S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 63Section number Title Page48.7.21 Lower Bit Rate Support............................................................................................................................... 254148.7.22 PE Data Memory (PE DRAM).................................................................................................................... 254248.7.23 CHI Lookup-Table Memory (CHI LRAM)................................................................................................. 254448.7.24 Memory Content Fault Detection................................................................................................................ 254548.7.25 Memory Fault Injection............................................................................................................................... 255048.7.26 StopWatch function......................................................................................................................................255348.8 Application Information................................................................................................................................................255548.8.1 Module Configuration..................................................................................................................................255548.8.2 Initialization Sequence.................................................................................................................................255648.8.3 Memory Fault Injection out of POC:default config.....................................................................................255848.8.4 Shut Down Sequence................................................................................................................................... 255948.8.5 Number of Usable Message Buffers............................................................................................................ 255948.8.6 Protocol Control Command Execution........................................................................................................ 256048.8.7 Message Buffer Search On Simple Message Buffer Configuration............................................................ 2561Chapter 49Secure Digital Host Controller (uSDHC)49.1 uSDHC Chip-specific information............................................................................................................................... 256549.2 Introduction...................................................................................................................................................................256649.2.1 Overview......................................................................................................................................................256649.3 Memory Map/Register Definition.................................................................................................................................257049.3.1 DMA System Address (uSDHC_S_ADDR)................................................................................................257249.3.2 Block Attributes (uSDHC_BLK_ATT)....................................................................................................... 257249.3.3 Command Argument (uSDHC_CMD_ARG)..............................................................................................257349.3.4 Command Transfer Type (uSDHC_CMD_XFR_TYP).............................................................................. 257449.3.5 Command Response0 (uSDHC_CMD_RSP0)............................................................................................ 257749.3.6 Command Response1 (uSDHC_CMD_RSP1)............................................................................................ 257849.3.7 Command Response2 (uSDHC_CMD_RSP2)............................................................................................ 257849.3.8 Command Response3 (uSDHC_CMD_RSP3)............................................................................................ 257949.3.9 Data Buffer Access Port (uSDHC_DATA_BUFF_ACC_PORT)...............................................................2580S32V234 Reference Manual, Rev. 5, 11/201964 NXP SemiconductorsSection number Title Page49.3.10 Present State (uSDHC_PRES_STATE).......................................................................................................258049.3.11 Protocol Control (uSDHC_PROT_CTRL).................................................................................................. 258649.3.12 System Control (uSDHC_SYS_CTRL).......................................................................................................259049.3.13 Interrupt Status (uSDHC_INT_STATUS)...................................................................................................259349.3.14 Interrupt Status Enable (uSDHC_INT_STATUS_EN)............................................................................... 259849.3.15 Interrupt Signal Enable (uSDHC_INT_SIGNAL_EN)............................................................................... 260249.3.16 Auto CMD12 Error Status (uSDHC_AUTOCMD12_ERR_STATUS)......................................................260449.3.17 Host Controller Capabilities (uSDHC_HOST_CTRL_CAP)......................................................................260849.3.18 Watermark Level (uSDHC_WTMK_LVL).................................................................................................261049.3.19 Mixer Control (uSDHC_MIX_CTRL)........................................................................................................ 261149.3.20 Force Event (uSDHC_FORCE_EVENT)....................................................................................................261349.3.21 ADMA Error Status Register (uSDHC_ADMA_ERR_STATUS)............................................................. 261649.3.22 ADMA System Address (uSDHC_ADMA_SYS_ADDR)......................................................................... 261849.3.23 Vendor Specific Register (uSDHC_VEND_SPEC).................................................................................... 261949.3.24 MMC Boot Register (uSDHC_MMC_BOOT)............................................................................................262249.3.25 Vendor Specific 2 Register (uSDHC_VEND_SPEC2)............................................................................... 262449.3.26 Host Controller Version (uSDHC_HOST_CTRL_VER)............................................................................ 262549.4 Functional Description..................................................................................................................................................262649.4.1 Data Buffer...................................................................................................................................................262649.4.2 DMA AHB Interface....................................................................................................................................263249.4.3 Register Bank ..............................................................................................................................................263849.4.4 Clock and Reset Manager............................................................................................................................ 264049.4.5 Clock Generator........................................................................................................................................... 264149.4.6 SDIO Card Interrupt.....................................................................................................................................264149.4.7 Card Insertion and Removal Detection........................................................................................................264349.4.8 Power Management and Wake Up Events...................................................................................................264449.5 Initialization/Application of uSDHC............................................................................................................................ 264549.5.1 Command Send and Response Receive Basic Operation............................................................................ 264549.5.2 Card Identification Mode............................................................................................................................. 2646S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 65Section number Title Page49.5.3 Card Access..................................................................................................................................................265249.5.4 Switch Function........................................................................................................................................... 266149.5.5 ADMA Operation........................................................................................................................................ 266349.6 Commands for MMC/SD/SDIO................................................................................................................................... 266549.7 Software Restrictions....................................................................................................................................................267049.7.1 Initialization Active......................................................................................................................................267049.7.2 Software Polling Procedure......................................................................................................................... 267049.7.3 Suspend Operation....................................................................................................................................... 267049.7.4 Data Length Setting..................................................................................................................................... 267049.7.5 (A)DMA Address Setting............................................................................................................................ 267149.7.6 Data Port Access.......................................................................................................................................... 267149.7.7 Change Clock Frequency............................................................................................................................. 267149.7.8 Multi-block Read......................................................................................................................................... 2671Chapter 50PCI Express (PCIe)50.1 PCIe Chip Specific Information....................................................................................................................................267350.1.1 GIC134 interrupt.......................................................................................................................................... 267350.2 Register Configuration for PCIe Base Spec..................................................................................................................267450.3 Introduction...................................................................................................................................................................267450.3.1 Terms and Abbreviations............................................................................................................................. 267450.3.2 Overview......................................................................................................................................................267650.3.3 Modes of Operation..................................................................................................................................... 268050.4 External (Link Interface) Signal Descriptions.............................................................................................................. 268150.5 PCIe CTRL EP Mode Memory Map/Register Definition............................................................................................ 268250.5.1 Device ID and Vendor ID Register (PCIE_EP_DeviceID)......................................................................... 268450.5.2 Command and Status Register (PCIE_EP_Command)............................................................................... 268650.5.3 PCI Express Revision ID Register (PCIE_EP_Revision_ID)......................................................................268950.5.4 BIST Register (PCIE_EP_BIST)................................................................................................................. 269150.5.5 Base Address 0 (PCIE_EP_BAR0)..............................................................................................................2692S32V234 Reference Manual, Rev. 5, 11/201966 NXP SemiconductorsSection number Title Page50.5.6 Base Address 1 (PCIE_EP_BAR1)..............................................................................................................269450.5.7 Base Address 2 (PCIE_EP_BAR2)..............................................................................................................269550.5.8 Base Address 3 (PCIE_EP_BAR3)..............................................................................................................269650.5.9 CardBus CIS Pointer Register (PCIE_EP_CISP)........................................................................................ 269650.5.10 Subsystem ID and Subsystem Vendor ID Register (PCIE_EP_SSID)........................................................269750.5.11 Expansion ROM Base Address Register (PCIE_EP_EROMBAR).............................................................269750.5.12 Capability Pointer Register (PCIE_EP_CAPPR)........................................................................................ 269850.5.13 Interrupt Line and Pin Register (PCIE_EP_ILR)........................................................................................ 269850.5.14 Power Management Capability ID Register (PCIE_EP_PMCIDR)............................................................ 269950.5.15 Power Management Capabilities Register (PCIE_EP_PMCR)................................................................... 269950.5.16 Power Management Status and Control Register (PCIE_EP_PMSCR)...................................................... 270050.5.17 PCI Express MSI Message Capability ID Register (PCIE_EP_MSI_MCIDR).......................................... 270150.5.18 PCI Express MSI Message Control Register (PCIE_EP_MSI_MCR)........................................................ 270250.5.19 PCI Express MSI Message Address Register (PCIE_EP_MSI_MADDR)................................................. 270350.5.20 PCI Express MSI Message Upper Address Register (PCIE_EP_MSI_MUADDR)................................... 270350.5.21 PCI Express MSI Message Data Register (PCIE_EP_MSI_MDATR)....................................................... 270450.5.22 Capability ID Register (PCIE_EP_CIDR)...................................................................................................270450.5.23 PCI Express Capabilities Register (PCIE_EP_CR)..................................................................................... 270450.5.24 PCI Express Device Capabilities Register (PCIE_EP_DCR)......................................................................270550.5.25 PCI Express Device Control Register (PCIE_EP_DCTRLR)..................................................................... 270650.5.26 PCI Express Device Status Register (PCIE_EP_DSR)................................................................................270750.5.27 PCI Express Link Capabilities Register (PCIE_EP_LCR).......................................................................... 270950.5.28 PCI Express Link Control Register (PCIE_EP_CTRLR)............................................................................271150.5.29 PCI Express Link Status Register (PCIE_EP_SR)...................................................................................... 271250.5.30 PCI Express Slot Capabilities Register (PCIE_EP_SCR)........................................................................... 271350.5.31 PCI Express Slot Control Register (PCIE_EP_SCTRLR)...........................................................................271450.5.32 PCI Express Slot Status Register (PCIE_EP_SSR)..................................................................................... 271650.5.33 Root Control Register (PCIE_EP_RCR)..................................................................................................... 271750.5.34 PCI Express Root Status Register (PCIE_EP_RSR)................................................................................... 2718S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 67Section number Title Page50.5.35 PCI Express Device Capabilities 2 Register (PCIE_EP_DC_2)................................................................. 271950.5.36 PCI Express Device Control 2 Register (PCIE_EP_DCTR_2)................................................................... 271950.5.37 PCI Express Link Capabilities 2 Register (PCIE_EP_LC_2)......................................................................272150.5.38 PCI Express Link Control 2 Register (PCIE_EP_LCTR_2)....................................................................... 272250.5.39 PCI Express Link Status 2 Register (PCIE_EP_LS_2)............................................................................... 272350.5.40 AER Capability Header (PCIE_EP_AER).................................................................................................. 272350.5.41 Uncorrectable Error Status Register (PCIE_EP_UESR)............................................................................. 272550.5.42 Uncorrectable Error Mask Register (PCIE_EP_UEMR).............................................................................272850.5.43 Uncorrectable Error Severity Register (PCIE_EP_UESevR)......................................................................273050.5.44 Correctable Error Status Register (PCIE_EP_CESR)................................................................................. 273250.5.45 Correctable Error Mask Register (PCIE_EP_CEMR)................................................................................. 273450.5.46 Advanced Capabilities and Control Register (PCIE_EP_ACCR)............................................................... 273650.5.47 PCI Express Header Log Register 1 (PCIE_EP_Header_Log_Register_DWORD1)................................. 273850.5.48 PCI Express Header Log Register 2 (PCIE_EP_Header_Log_Register_DWORD2)................................. 273950.5.49 PCI Express Header Log Register 3 (PCIE_EP_Header_Log_Register_DWORD3)................................. 273950.5.50 PCI Express Header Log Register 4 (PCIE_EP_Header_Log_Register_DWORD4)................................. 274050.5.51 BAR 0 Mask Register (PCIE_EP_MASK0)................................................................................................274050.5.52 BAR 1 Mask Register (PCIE_EP_MASK1)................................................................................................274250.5.53 BAR 2 Mask Register (PCIE_EP_MASK2)................................................................................................274350.5.54 BAR 3 Mask Register (PCIE_EP_MASK3)................................................................................................274450.5.55 Expansion ROM BAR Mask Register (PCIE_EP_EROMMASK)............................................................. 274550.6 PCIe CTRL RC Mode Memory Map/Register Definition............................................................................................274650.6.1 Device ID and Vendor ID Register (PCIE_RC_DeviceID).........................................................................274850.6.2 Command and Status Register (PCIE_RC_Command)...............................................................................274950.6.3 BIST Register (PCIE_RC_BIST)................................................................................................................ 275250.6.4 Base Address 0 (PCIE_RC_BAR0).............................................................................................................275350.6.5 Base Address 1 (PCIE_RC_BAR1).............................................................................................................275550.6.6 Bus Number Registers (PCIE_RC_BNR)....................................................................................................275550.6.7 I/O Base Limit Secondary Status Register (PCIE_RC_IOBLSSR).............................................................2757S32V234 Reference Manual, Rev. 5, 11/201968 NXP SemiconductorsSection number Title Page50.6.8 Memory Base and Memory Limit Register (PCIE_RC_MEM_BLR)........................................................ 275950.6.9 Prefetchable Memory Base and Limit Register (PCIE_RC_PREF_MEM_BLR).......................................275950.6.10 Prefetchable Base Upper 32 Bits Register (PCIE_RC_PREF_BASE_U32)...............................................276050.6.11 Prefetchable Limit Upper 32 Bits Register (PCIE_RC_PREF_LIM_U32).................................................276050.6.12 I/O Base and Limit Upper 16 Bits Register (PCIE_RC_IO_BASE_LIM_U16).........................................276150.6.13 Capability Pointer Register (PCIE_RC_CAPPR)........................................................................................276150.6.14 Expansion ROM Base Address Register (PCIE_RC_EROMBAR)............................................................ 276250.6.15 PCI Express Interrupt Line Register (PCIE_RC_Interrupt_Line_Register)................................................276250.6.16 Power Management Capability Register (PCIE_RC_PMCR).....................................................................276350.6.17 Power Management Control and Status Register (PCIE_RC_PMCSR)..................................................... 276650.6.18 PCI Express Capability ID Register (PCIE_RC_CIDR)............................................................................. 276950.6.19 Device Capabilities Register (PCIE_RC_DCR).......................................................................................... 277050.6.20 Device Control Register (PCIE_RC_DConR).............................................................................................277250.6.21 Link Capabilities Register (PCIE_RC_LCR).............................................................................................. 277650.6.22 Link Control and Status Register (PCIE_RC_LCSR)................................................................................. 277950.6.23 Slot Capabilities Register (PCIE_RC_SCR)................................................................................................278350.6.24 Slot Control and Status Register (PCIE_RC_SCSR)...................................................................................278650.6.25 Root Control and Capabilities Register (PCIE_RC_RCCR)....................................................................... 278850.6.26 Root Status Register (PCIE_RC_RSR)........................................................................................................278950.6.27 Device Capabilities 2 Register (PCIE_RC_DCR2)..................................................................................... 279150.6.28 Device Control and Status 2 Register (PCIE_RC_DCSR2)........................................................................ 279250.6.29 Link Capabilities 2 Register (PCIE_RC_LCR2)......................................................................................... 279450.6.30 Link Control and Status 2 Register (PCIE_RC_LCSR2)............................................................................ 279650.6.31 AER Capability Header (PCIE_RC_AER)..................................................................................................279950.6.32 Uncorrectable Error Status Register (PCIE_RC_UESR).............................................................................280150.6.33 Uncorrectable Error Mask Register (PCIE_RC_UEMR)............................................................................ 280450.6.34 Uncorrectable Error Severity Register (PCIE_RC_UESevR)..................................................................... 280650.6.35 Correctable Error Status Register (PCIE_RC_CESR).................................................................................280850.6.36 Correctable Error Mask Register (PCIE_RC_CEMR)................................................................................ 2810S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 69Section number Title Page50.6.37 Advanced Error Capabilities and Control Register (PCIE_RC_AECCR)...................................................281250.6.38 PCI Express Header Log Register 1 (PCIE_RC_Header_Log_Register_DWORD1)................................ 281450.6.39 PCI Express Header Log Register 2 (PCIE_RC_Header_Log_Register_DWORD2)................................ 281550.6.40 PCI Express Header Log Register 3 (PCIE_RC_Header_Log_Register_DWORD3)................................ 281550.6.41 PCI Express Header Log Register 4 (PCIE_RC_Header_Log_Register_DWORD4)................................ 281650.6.42 Root Error Command Register (PCIE_RC_RECR).................................................................................... 281750.6.43 Root Error Status Register (PCIE_RC_RESR)............................................................................................281850.6.44 Error Source Identification Register (PCIE_RC_ESIR)..............................................................................282050.6.45 BAR 0 Mask Register (PCIE_RC_MASK0)............................................................................................... 282050.6.46 BAR 1 Mask Register (PCIE_RC_MASK1)............................................................................................... 282350.6.47 Expansion ROM BAR Mask Register (PCIE_RC_EROMMASK)............................................................ 282350.7 PCIe CTRL Port Logic Memory Map/Register Definition.......................................................................................... 282450.7.1 Ack Latency Timer and Replay Timer Register (PCIE_PL_ALTRTR)......................................................282650.7.2 Vendor Specific DLLP Register (PCIE_PL_VSDR)...................................................................................282750.7.3 Port Force Link Register (PCIE_PL_PFLR)............................................................................................... 282750.7.4 Ack Frequency and L0-L1 ASPM Control Register (PCIE_PL_AFLACR)...............................................282850.7.5 Port Link Control Register (PCIE_PL_PLCR)............................................................................................283150.7.6 Lane Skew Register (PCIE_PL_LSR)......................................................................................................... 283350.7.7 Timer Control and Max Function Number Register (PCIE_PL_TIMER_CTRL_MAX_NUM)................283450.7.8 Symbol Timer Register and Filter Mask Register 1 (PCIE_PL_STRFM1)................................................ 283550.7.9 Filter Mask Register 2 (PCIE_PL_STRFM2)..............................................................................................283650.7.10 AMBA Multiple Outbound Decomposed NP Sub-Requests Control Register (PCIE_PL_AMODNPSR) 283750.7.11 Debug Register 0 (PCIE_PL_DEBUG0).....................................................................................................283850.7.12 Debug Register 1 (PCIE_PL_DEBUG1).....................................................................................................283850.7.13 Transmit Posted FC Credit Status Register (PCIE_PL_TPFCSR).............................................................. 283850.7.14 Transmit Non-Posted FC Credit Status Register (PCIE_PL_TNFCSR)..................................................... 283950.7.15 Transmit Completion FC Credit Status Register (PCIE_PL_TCFCSR)..................................................... 284050.7.16 Queue Status Register (PCIE_PL_QSR)..................................................................................................... 284150.7.17 Gen2 Control Register (PCIE_PL_G2CR).................................................................................................. 2844S32V234 Reference Manual, Rev. 5, 11/201970 NXP SemiconductorsSection number Title Page50.7.18 PHY Status (PCIE_PL_PHY_STATUS).....................................................................................................284550.7.19 PHY Control (PCIE_PL_PHY_CTRL)....................................................................................................... 284650.7.20 Master Response Composer Control Register 0 (PCIE_PL_MRCCR0)..................................................... 284650.7.21 Master Response Composer Control Register 1 (PCIE_PL_MRCCR1)..................................................... 284750.7.22 MSI Controller Address (PCIE_PL_MSICA)............................................................................................. 284850.7.23 MSI Controller Upper Address (PCIE_PL_MSICUA)............................................................................... 284850.7.24 MSI Controller Interrupt n Enable (PCIE_PL_MSICIn_ENB)...................................................................284950.7.25 MSI Controller Interrupt n Mask (PCIE_PL_MSICIn_MASK)..................................................................284950.7.26 MSI Controller Interrupt nStatus (PCIE_PL_MSICInn_STATUS)............................................................ 285050.7.27 MSI Controller General Purpose IO Register (PCIE_PL_MSICGPIO)......................................................285050.7.28 iATM Viewport Register (PCIE_PL_iATMVR).........................................................................................285050.7.29 iATM Region Control 1 Register (PCIE_PL_iATMRC1).......................................................................... 285250.7.30 iATM Region Control 2 Register (PCIE_PL_iATMRC2).......................................................................... 285450.7.31 iATM Region Lower Base Address Register (PCIE_PL_iATMRLBA).....................................................285750.7.32 iATM Region Upper Base Address Register (PCIE_PL_iATMRUBA).....................................................285850.7.33 iATM Region Limit Address Register (PCIE_PL_iATMRLA)..................................................................285850.7.34 iATM Region Lower Target Address Register (PCIE_PL_iATMRLTA).................................................. 285850.7.35 iATM Region Upper Target Address Register (PCIE_PL_iATMRUTA).................................................. 285950.8 Functional Description..................................................................................................................................................285950.8.1 Transaction Layer........................................................................................................................................ 286050.8.2 Data Link Layer........................................................................................................................................... 286150.8.3 MAC Layer.................................................................................................................................................. 286150.8.4 Architecture..................................................................................................................................................286250.9 Initialization/Application Information..........................................................................................................................286450.9.1 Initial start-up programming guide ............................................................................................................. 286450.9.2 L2 entry and exit procedures........................................................................................................................286550.10 Embedded DMA Controller..........................................................................................................................................286550.10.1 Overview......................................................................................................................................................286550.10.2 Feature List.................................................................................................................................................. 2866S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 71Section number Title Page50.10.3 Limitations................................................................................................................................................... 286750.10.4 DMA Architecture....................................................................................................................................... 286850.10.5 Interrupts and Error Handling...................................................................................................................... 287050.10.6 Using the DMA............................................................................................................................................288050.10.7 Programming Examples...............................................................................................................................288550.10.8 Advanced DMA Information and Operation............................................................................................... 289550.10.9 PCIe Registers (DMA).................................................................................................................................290150.11 PCIe2 PHY Overview...................................................................................................................................................293950.12 PCIe2 PHY Features.....................................................................................................................................................294050.12.1 Standards Compliance..................................................................................................................................294050.12.2 PHY Features............................................................................................................................................... 294050.13 PCIe2 PHY Functional Description..............................................................................................................................294050.13.1 Clocks and Resets........................................................................................................................................ 2940Chapter 51Analog-to-Digital Converter (SAR-ADC)51.1 Chip specific SAR-ADC information...........................................................................................................................294351.1.1 SAR-ADC channels..................................................................................................................................... 294351.1.2 Channel specific configurations...................................................................................................................294451.1.3 Self-test........................................................................................................................................................ 294551.2 Introduction...................................................................................................................................................................294551.3 Overview.......................................................................................................................................................................294551.3.1 Interfaces......................................................................................................................................................294651.3.2 Submodules..................................................................................................................................................294651.3.3 Clock and Reset........................................................................................................................................... 294651.3.4 Special channels...........................................................................................................................................294751.4 Feature list.....................................................................................................................................................................294851.5 Functional description...................................................................................................................................................294851.5.1 Conversion................................................................................................................................................... 294851.5.2 Normal Conversion mode............................................................................................................................ 2949S32V234 Reference Manual, Rev. 5, 11/201972 NXP SemiconductorsSection number Title Page51.5.3 Injected Conversion mode........................................................................................................................... 295251.5.4 Abort of conversion..................................................................................................................................... 295351.5.5 ADC clock prescaler and sample time settings............................................................................................295451.5.6 Presampling..................................................................................................................................................295551.5.7 Programmable analog watchdog..................................................................................................................295651.5.8 DMA functionality.......................................................................................................................................295851.5.9 Interrupts...................................................................................................................................................... 295951.5.10 Power Down mode.......................................................................................................................................296251.5.11 Auto-clock-off mode....................................................................................................................................296351.5.12 Calibration ...................................................................................................................................................296351.5.13 Self-test ....................................................................................................................................................... 296551.5.14 Conversion time........................................................................................................................................... 297651.5.15 Conversion data processing......................................................................................................................... 298051.5.16 User defined offset and gain values............................................................................................................. 298051.6 Programming sequences............................................................................................................................................... 298251.6.1 Running calibration......................................................................................................................................298251.6.2 Running Normal conversion........................................................................................................................ 298351.6.3 Running Injected conversion....................................................................................................................... 298451.6.4 Running self-test.......................................................................................................................................... 298451.7 Register Description......................................................................................................................................................298551.7.1 Main Configuration Register (SAR_ADC_MCR).......................................................................................298851.7.2 Main Status Register (SAR_ADC_MSR)....................................................................................................299251.7.3 Interrupt Status Register (SAR_ADC_ISR)................................................................................................ 299551.7.4 Channel Pending Register (SAR_ADC_CEOCFR0).................................................................................. 299551.7.5 Channel Pending Register 1 (SAR_ADC_CEOCFR1)............................................................................... 299751.7.6 Interrupt Mask Register (SAR_ADC_IMR)................................................................................................ 299951.7.7 Channel Interrupt Mask Register 0 (SAR_ADC_CIMR0).......................................................................... 300051.7.8 Channel Interrupt Mask Register 1 (SAR_ADC_CIMR1).......................................................................... 300151.7.9 Watchdog Threshold Interrupt Status Register (SAR_ADC_WTISR)........................................................3003S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 73Section number Title Page51.7.10 Watchdog Threshold Interrupt Mask Register (SAR_ADC_WTIMR)....................................................... 300551.7.11 DMAE Register (SAR_ADC_DMAE)........................................................................................................300851.7.12 DMA Register 0 (SAR_ADC_DMAR0)..................................................................................................... 300851.7.13 DMA Register 1 (SAR_ADC_DMAR1)..................................................................................................... 301051.7.14 Analog Watchdog Threshold Register 0 (SAR_ADC_THRHLR0)............................................................ 301251.7.15 Analog Watchdog Threshold Register 1 (SAR_ADC_THRHLR1)............................................................ 301251.7.16 Analog Watchdog Threshold Register 2 (SAR_ADC_THRHLR2)............................................................ 301351.7.17 Analog Watchdog Threshold Register 2 (SAR_ADC_THRHLR3)............................................................ 301351.7.18 Presampling Control Register (SAR_ADC_PSCR).................................................................................... 301451.7.19 Presampling Register 0 (SAR_ADC_PSR0)............................................................................................... 301451.7.20 Presampling Register 1 (SAR_ADC_PSR1)............................................................................................... 301651.7.21 Conversion Timing Register 0 (SAR_ADC_CTR0)................................................................................... 301851.7.22 Conversion Timing Register 2 (SAR_ADC_CTR1)................................................................................... 301851.7.23 Normal Conversion Mask Register (SAR_ADC_NCMR0)........................................................................ 301851.7.24 Normal Conversion Mask Register (SAR_ADC_NCMR1)........................................................................ 302051.7.25 Injected Conversion Mask Register (SAR_ADC_JCMR0).........................................................................302151.7.26 Injected Conversion Mask Register (SAR_ADC_JCMR1).........................................................................302351.7.27 User OFFSET and Gain Register (SAR_ADC_USROFSGN).................................................................... 302451.7.28 Power Down Exit Delay Register (SAR_ADC_PDEDR)........................................................................... 302551.7.29 Channel n Data Register (SAR_ADC_CDRn)............................................................................................ 302551.7.30 Channel n Data Register (SAR_ADC_CDRn)............................................................................................ 302751.7.31 Analog Watchdog Threshold Register 4 (SAR_ADC_THRHLR4)............................................................ 302851.7.32 Analog Watchdog Threshold Register 5 (SAR_ADC_THRHLR5)............................................................ 302851.7.33 Analog Watchdog Threshold Register 6 (SAR_ADC_THRHLR6)............................................................ 302951.7.34 Analog Watchdog Threshold Register 7 (SAR_ADC_THRHLR7)............................................................ 302951.7.35 Channel Watchdog Select Register (SAR_ADC_CWSELR0)....................................................................303051.7.36 Channel Watchdog Select Register (SAR_ADC_CWSELR4)....................................................................303251.7.37 Channel Watchdog Enable Register (SAR_ADC_CWENR0).................................................................... 303451.7.38 Channel Watchdog Enable Register (SAR_ADC_CWENR1).................................................................... 3036S32V234 Reference Manual, Rev. 5, 11/201974 NXP SemiconductorsSection number Title Page51.7.39 Analog Watchdog Out of Range Register (SAR_ADC_AWORR0)...........................................................303751.7.40 Analog Watchdog Out of Range Register (SAR_ADC_AWORR1)...........................................................303951.7.41 Self-Test Configuration Register 1 (SAR_ADC_STCR1).......................................................................... 304151.7.42 Self-Test Configuration Register 2 (SAR_ADC_STCR2).......................................................................... 304251.7.43 Self-Test Configuration Register 3 (SAR_ADC_STCR3).......................................................................... 304551.7.44 Self-Test Baud Rate Register (SAR_ADC_STBRR).................................................................................. 304651.7.45 Self-Test Status Register 1 (SAR_ADC_STSR1)....................................................................................... 304751.7.46 Self-Test Status Register 2 (SAR_ADC_STSR2)....................................................................................... 305051.7.47 Self-Test Status Register 3 (SAR_ADC_STSR3)....................................................................................... 305151.7.48 Self-Test Status Register 4 (SAR_ADC_STSR4)....................................................................................... 305151.7.49 Self-Test Data Register 1 (SAR_ADC_STDR1)......................................................................................... 305251.7.50 Self-Test Data Register 2 (SAR_ADC_STDR2)......................................................................................... 305351.7.51 Self-Test Analog Watchdog Register (SAR_ADC_STAW0R)...................................................................305451.7.52 Self-Test Analog Watchdog Register (SAR_ADC_STAW1AR)................................................................305551.7.53 Self-Test Analog Watchdog Register 1B (SAR_ADC_STAW1BR).......................................................... 305651.7.54 Self-Test Analog Watchdog Register 2 (SAR_ADC_STAW2R)................................................................305751.7.55 Self-Test Analog Watchdog Register 3 (SAR_ADC_STAW3R)................................................................305751.7.55 Self-Test Analog Watchdog Register 4 (SAR_ADC_STAW4R)................................................................305851.7.56 Self-Test Analog Watchdog Register 5 (SAR_ADC_STAW5R)................................................................305951.7.57 Calibration Status register (SAR_ADC_CALSTAT).................................................................................. 306051.8 Input impedance versus ADC speed.............................................................................................................................3063Chapter 52Temperature Sensor52.1 Chip-specific TSENS Information................................................................................................................................306552.2 Introduction...................................................................................................................................................................306552.2.1 Overview......................................................................................................................................................306552.2.2 Features........................................................................................................................................................ 306652.2.3 Modes of Operation..................................................................................................................................... 306752.3 TMU memory map and registers.................................................................................................................................. 3067S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 75Section number Title Page52.3.1 Mode Register (TMU_MR)......................................................................................................................... 306952.3.2 Status Register (TMU_SR).......................................................................................................................... 307052.3.3 Monitor Temperature Measurement Interval Register (TMU_MTMIR).....................................................307152.3.4 Interrupt Enable Register (TMU_IER)........................................................................................................ 307252.3.5 Interrupt Detect Register (TMU_IDR)........................................................................................................ 307352.3.6 Monitor High Temperature Capture Register (TMU_MHTCR)................................................................. 307452.3.7 Monitor Low Temperature Capture Register (TMU_MLTCR).................................................................. 307552.3.8 Monitor High Temperature Immediate Threshold Register (TMU_MHTITR)...........................................307552.3.9 Monitor High Temperature Average Threshold Register (TMU_MHTATR).............................................307652.3.10 Monitor High Temperature Average Critical Threshold Register (TMU_MHTACTR).............................307752.3.11 Temperature Configuration Register (TMU_TCFGR)................................................................................ 307752.3.12 Sensor Configuration Register (TMU_SCFGR)..........................................................................................307852.3.13 Report Immediate Temperature Site Register (TMU_RITSR)....................................................................307952.3.14 Report Average Temperature Site Register (TMU_RATSR)......................................................................307952.3.15 Engineering Use Mode Register (TMU_EUMR)........................................................................................ 308052.4 Functional Description..................................................................................................................................................308052.4.1 Monitoring................................................................................................................................................... 308152.4.2 Reporting......................................................................................................................................................308152.5 Initialization information.............................................................................................................................................. 3082Chapter 532D-ACE53.1 2D-ACE QoS................................................................................................................................................................ 308553.2 Introduction...................................................................................................................................................................308553.2.1 Overview......................................................................................................................................................308653.2.2 Features........................................................................................................................................................ 308853.2.3 Modes of operation...................................................................................................................................... 308953.3 External Signal Description.......................................................................................................................................... 308953.3.1 Overview......................................................................................................................................................308953.3.2 Detailed Signal Descriptions........................................................................................................................3089S32V234 Reference Manual, Rev. 5, 11/201976 NXP SemiconductorsSection number Title Page53.4 Memory Map................................................................................................................................................................ 309053.5 Memory Map and Registers..........................................................................................................................................309053.5.1 Control Descriptor Cursor 1 Register (DCU_CTRLDESCCURSOR1)......................................................309653.5.2 Control Descriptor Cursor 2 Register (DCU_CTRLDESCCURSOR2)......................................................309753.5.3 Control Descriptor Cursor 3 Register (DCU_CTRLDESCCURSOR3)......................................................309853.5.4 Mode Register (DCU_MODE).................................................................................................................... 309953.5.5 Background Register (DCU_BGND).......................................................................................................... 310153.5.6 Display Size Register (DCU_DISP_SIZE)..................................................................................................310253.5.7 Horizontal Sync Parameter Register (DCU_HSYN_PARA)...................................................................... 310253.5.8 Vertical Sync Parameter Register (DCU_VSYN_PARA)...........................................................................310353.5.9 Synchronize Polarity Register (DCU_SYNPOL)........................................................................................ 310453.5.10 Threshold Register (DCU_THRESHOLD)................................................................................................. 310553.5.11 Interrupt Status Register (DCU_INT_STATUS).........................................................................................310653.5.12 Interrupt Mask Register (DCU_INT_MASK)............................................................................................. 310953.5.13 COLBAR_1 Register (DCU_COLBAR_1).................................................................................................311153.5.14 COLBAR_2 Register (DCU_COLBAR_2).................................................................................................311253.5.15 COLBAR_3 Register (DCU_COLBAR_3).................................................................................................311253.5.16 COLBAR_4 Register (DCU_COLBAR_4).................................................................................................311353.5.17 COLBAR_5 Register (DCU_COLBAR_5).................................................................................................311453.5.18 COLBAR_6 Register (DCU_COLBAR_6).................................................................................................311453.5.19 COLBAR_7 Register (DCU_COLBAR_7).................................................................................................311553.5.20 COLBAR_8 Register (DCU_COLBAR_8).................................................................................................311553.5.21 Divide Ratio Register (DCU_DIV_RATIO)............................................................................................... 311653.5.22 Sign Calculation 1 Register (DCU_SIGN_CALC_1)................................................................................. 311753.5.23 Sign Calculation 2 Register (DCU_SIGN_CALC_2)................................................................................. 311853.5.24 CRC Value Register (DCU_CRC_VAL).................................................................................................... 311853.5.25 Parameter Error Status 1 Register (DCU_PARR_ERR_STATUS1).......................................................... 311953.5.26 Parameter Error Status 3 Register (DCU_PARR_ERR_STATUS3).......................................................... 311953.5.27 Mask Parameter Error Status 1 Register (DCU_MASK_PARR_ERR_STATUS1)................................... 3120S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 77Section number Title Page53.5.28 Mask Parameter Error Status 3 Register (DCU_MASK_PARR_ERR_STATUS3)................................... 312153.5.29 Threshold Input 1 Register (DCU_THRESHOLD_INP_BUF_1)...............................................................312253.5.30 LUMA Component Register (DCU_LUMA_COMP).................................................................................312353.5.31 Red Chroma Components Register (DCU_CHROMA_RED).................................................................... 312453.5.32 Green Chroma Components Register (DCU_CHROMA_GREEN)........................................................... 312453.5.33 Blue Chroma Components Register (DCU_CHROMA_BLUE).................................................................312553.5.34 CRC Position Register (DCU_CRC_POS)..................................................................................................312553.5.35 Layer Interpolation Enable Register (DCU_LYR_INTPOL_EN)...............................................................312653.5.36 Layer Luminance Component Register (DCU_LYR_LUMA_COMP)...................................................... 312753.5.37 Layer Chroma Red Register (DCU_LYR_CHRM_RED)...........................................................................312853.5.38 Layer Chroma Green Register (DCU_LYR_CHRM_GRN)....................................................................... 312853.5.39 Layer Chroma Blue Register (DCU_LYR_CHRM_BLUE)....................................................................... 312953.5.40 Update Mode Register (DCU_UPDATE_MODE)......................................................................................313053.5.41 Underrun Register (DCU_UNDERRUN)....................................................................................................313153.5.42 Frame CRC Control (DCU_FRM_CRC_CTRL)........................................................................................ 313153.5.43 Frame CRC Value (DCU_FRM_CRC_VAL)............................................................................................. 313253.5.44 QoS Level (DCU_TX_ESCAL_LVL).........................................................................................................313253.5.45 Global Protection Register (DCU_GPR)..................................................................................................... 313353.5.46 Soft Lock Bit Layer 0 Register (DCU_SLR_L0)........................................................................................ 313453.5.47 Soft Lock Bit Layer 1 Register (DCU_SLR_L1)........................................................................................ 313653.5.48 Soft Lock Display Size Register (DCU_SLR_DISP_SIZE)........................................................................313953.5.49 Soft Lock Hsync/Vsync Parameter Register (DCU_SLR_HVSYNC_PARA)........................................... 314053.5.50 Soft Lock POL Register (DCU_SLR_POL)................................................................................................314153.5.51 Soft Lock L0 Transparency Register (DCU_SLR_L0_TRANSP).............................................................. 314253.5.52 Soft Lock L1 Transparency Register (DCU_SLR_L1_TRANSP).............................................................. 314453.5.53 Control Descriptor Layer 1 Register (DCU_CTRLDESCLn_1).................................................................314553.5.54 Control Descriptor Layer 2 Register (DCU_CTRLDESCLn_2).................................................................314653.5.55 Control Descriptor Layer 3 Register (DCU_CTRLDESCLn_3).................................................................314653.5.56 Control Descriptor Layer 4 Register (DCU_CTRLDESCLn_4).................................................................3147S32V234 Reference Manual, Rev. 5, 11/201978 NXP SemiconductorsSection number Title Page53.5.57 Control Descriptor Layer 5 Register (DCU_CTRLDESCLn_5).................................................................314953.5.58 Control Descriptor Layer 6 Register (DCU_CTRLDESCLn_6).................................................................315053.5.59 Control Descriptor Layer 8 Register (DCU_CTRLDESCLn_8).................................................................315153.5.60 Control Descriptor Layer 9 Register (DCU_CTRLDESCLn_9).................................................................315153.5.61 Control Descriptor Layer 10 Register (DCU_CTRLDESCLn_10).............................................................315253.6 Functional Description..................................................................................................................................................315353.6.1 TFT LCD panel configuration..................................................................................................................... 315353.6.2 Mode selection and background color......................................................................................................... 315653.6.3 Layer configuration and blending................................................................................................................ 315653.6.4 Hardware cursor...........................................................................................................................................317853.6.5 CLUT RAM................................................................................................................................................. 317953.6.6 Gamma correction........................................................................................................................................318053.6.7 Temporal Dithering......................................................................................................................................318153.7 Timing, Error and Interrupt Management.....................................................................................................................318253.7.1 Synchronizing to panel frame rate............................................................................................................... 318253.7.2 Managing the FIFOs and DMA activity...................................................................................................... 318353.7.3 Arbitration and DMA scheduling................................................................................................................ 318553.7.4 Error detection..............................................................................................................................................318653.7.5 Interrupt generation......................................................................................................................................318753.8 Register protection........................................................................................................................................................318853.8.1 Operation of scheme.................................................................................................................................... 318853.8.2 List of protected registers.............................................................................................................................318953.9 Safety Mode..................................................................................................................................................................318953.9.1 CRC Area Description................................................................................................................................. 319153.10 2D-ACE Initialization...................................................................................................................................................319353.11 Glossary........................................................................................................................................................................ 3194Chapter 54GC3000 Graphics Processing Unit (GC3000)54.1 Introduction...................................................................................................................................................................3195S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 79Section number Title Page54.2 GC3000 architecture..................................................................................................................................................... 319654.2.1 GPU 3D hardware features.......................................................................................................................... 319654.2.2 GPU core design description........................................................................................................................319654.2.3 GPU core API support and architecture features......................................................................................... 319854.2.4 OpenCL support...........................................................................................................................................319954.3 GC3000 driver architecture overview...........................................................................................................................319954.3.1 Graphics driver software stack.....................................................................................................................319954.3.2 3D rendering................................................................................................................................................ 320054.3.3 Commands and Data.................................................................................................................................... 320154.3.4 Threads and Contexts...................................................................................................................................320154.3.5 Driver GAL (Graphics Abstraction Layer)..................................................................................................3202Chapter 55DEC200 Compression/Decompression Engine55.1 Introduction...................................................................................................................................................................320355.2 Hardware features......................................................................................................................................................... 320455.2.1 Encode and decode hardware features......................................................................................................... 320455.3 Memory Map and Register Description........................................................................................................................320455.3.1 DEC200_gcregDECReadConfign............................................................................................................... 320755.3.2 DEC200_gcregDECWriteConfign...............................................................................................................320855.3.3 DEC200_gcregDECReadBufferBasen........................................................................................................ 320955.3.4 DEC200_gcregDECReadCacheBasen.........................................................................................................321055.3.5 DEC200_gcregDECWriteBufferBasen....................................................................................................... 321055.3.6 DEC200_gcregDECWriteCacheBasen........................................................................................................321055.3.7 DEC200_gcregDECControl.........................................................................................................................321155.3.8 DEC200_gcregDECIntrAcknowledge.........................................................................................................321355.3.9 DEC200_gcregDECIntrEnbl....................................................................................................................... 321455.3.10 DEC200_gcDECTotalReadsIn.................................................................................................................... 321555.3.11 DEC200_gcDECTotalWritesIn................................................................................................................... 321555.3.12 DEC200_gcDECTotalReadBurstsIn............................................................................................................3216S32V234 Reference Manual, Rev. 5, 11/201980 NXP SemiconductorsSection number Title Page55.3.13 DEC200_gcDECTotalWriteBurstsIn...........................................................................................................321655.3.14 DEC200_gcDECTotalReadsReqIn..............................................................................................................321655.3.15 DEC200_gcDECTotalWritesReqIn............................................................................................................. 321755.3.16 DEC200_gcDECTotalReadLastsIn............................................................................................................. 321755.3.17 DEC200_gcDECTotalWriteLastsIn.............................................................................................................321855.3.18 DEC200_gcDECTotalReadsOUT............................................................................................................... 321855.3.19 DEC200_gcDECTotalWritesOUT...............................................................................................................321855.3.20 DEC200_gcDECTotalReadBurstsOUT.......................................................................................................321955.3.21 DEC200_gcDECTotalWriteBurstsOUT......................................................................................................321955.3.22 DEC200_gcDECTotalReadsReqOUT......................................................................................................... 322055.3.23 DEC200_gcDECTotalWritesReqOUT........................................................................................................ 322055.3.24 DEC200_gcDECTotalReadLastsOUT.........................................................................................................322055.3.25 DEC200_gcDECTotalWriteLastsOUT........................................................................................................3221Chapter 56ADAS Camera Vision Flow56.1 Introduction...................................................................................................................................................................322356.2 Components and Data Flow..........................................................................................................................................322456.3 Use Case........................................................................................................................................................................3225Chapter 57APEX-CL Image Cognition Processor57.1 Chip-specific APEX-CL Information...........................................................................................................................322957.2 Introduction...................................................................................................................................................................322957.3 Overview.......................................................................................................................................................................322957.4 Feature Summary..........................................................................................................................................................322957.5 Acronyms and Abbreviations....................................................................................................................................... 323157.6 Global Software Interface.............................................................................................................................................323157.7 APU Architecture..........................................................................................................................................................323257.7.1 The Computational Units (CU)....................................................................................................................323357.7.2 CU Registers................................................................................................................................................ 3233S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 81Section number Title Page57.7.3 Shifter/Rotator..............................................................................................................................................323357.7.4 CU-to-CU Shifter.........................................................................................................................................323457.7.5 Multiplier..................................................................................................................................................... 323457.7.6 Load/Store Unit............................................................................................................................................323557.8 CMEM Interface........................................................................................................................................................... 323557.9 DMEM FIFO................................................................................................................................................................ 323657.10 DMA Subsystem...........................................................................................................................................................323657.11 Sequencer......................................................................................................................................................................323757.12 Horizontal Resizer/Scaler (HRSZ)............................................................................................................................... 323857.13 Features.........................................................................................................................................................................3238Chapter 58High Performance Shared Memory Interconnect (HPSMI)58.1 Chip-specific HPSMI information................................................................................................................................323958.1.1 AXI Master Connections............................................................................................................................. 323958.1.2 Stream DMA Master Connections...............................................................................................................324058.1.3 SRAM contents retention on a functional reset........................................................................................... 324158.2 Introduction...................................................................................................................................................................324158.3 Feature List................................................................................................................................................................... 324258.4 Block diagram...............................................................................................................................................................324358.5 Memory Map and Register Definition..........................................................................................................................324458.5.1 HPSMI Global Control Register (HPSMI_GBL_CTRL)............................................................................324958.5.2 HPSMI MPU Address Select 0 Register (HPSMI_MPU_SEL0)................................................................325058.5.3 HPSMI MPU Address Select 1 Register (HPSMI_MPU_SEL1)................................................................325058.5.4 HPSMI MPU Address Select 2 Register (HPSMI_MPU_SEL2)................................................................325158.5.5 HPSMI MPU Address Select 3 Register (HPSMI_MPU_SEL3)................................................................325158.5.6 HPSMI Stream DMA Master Priority Change Register (HPSMI_PRIO_CHANGE)................................ 325258.5.7 HPSMI LSB2AXI Master 0 Cycle counter Register (HPSMI_PROFILE_LSB2AXICYCCNTR_0)........325358.5.8 HPSMI LSB2AXI Master 1 Cycle Counter Value Register(HPSMI_PROFILE_LSB2AXICYCCNTR_1)........................................................................................... 3253S32V234 Reference Manual, Rev. 5, 11/201982 NXP SemiconductorsSection number Title Page58.5.9 HPSMI Profile Cycle Counter Overflow Register (HPSMI_PROFILE_CYCCNTR_OVF)......................325458.5.10 HPSMI AXI Profile Stop Register (HPSMI_PROFILE_STOP).................................................................325658.5.11 HPSMI Interrupt Enable 0 Register (HPSMI_INTR_EN0)........................................................................ 325758.5.12 HPSMI Interrupt Enable 1 Register (HPSMI_INTR_EN1)........................................................................ 325858.5.13 HPSMI AXI Profile Start Register (HPSMI_PROFILE_START)..............................................................326058.5.14 HPSMI AXI Profile Reset Register (HPSMI_PROFILE_RESET).............................................................326158.5.15 HPSMI AXI Profile Freeze Register (HPSMI_PROFILE_FREEZE).........................................................326358.5.16 HPSMI AXI Profile Decrement Value Register (HPSMI_PROFILE_DECVAL)......................................326458.5.17 HPSMI AXI Profile Decrement Counter Information Register(HPSMI_PROFILE_DECVAL_CNTRNUM)............................................................................................ 326558.5.18 HPSMI AXI Master 0 Read Port Profile Counter Value Register(HPSMI_PROFILE_AXIRDCNTRVAL_0)............................................................................................... 326658.5.19 HPSMI AXI Master 0 Write Port Profile Counter Value Register(HPSMI_PROFILE_AXIWRCNTRVAL_0).............................................................................................. 326658.5.20 HPSMI AXI Master 1 Read Port Profile Counter Value Register(HPSMI_PROFILE_AXIRDCNTRVAL_1)............................................................................................... 326758.5.21 HPSMI AXI Master 1 Write Port Profile Counter Value Register(HPSMI_PROFILE_AXIWRCNTRVAL_1).............................................................................................. 326758.5.22 HPSMI AXI Master 2 Read Port Profile Counter Value Register(HPSMI_PROFILE_AXIRDCNTRVAL_2)............................................................................................... 326858.5.23 HPSMI AXI Master 2 Write Port Profile Counter Value Register(HPSMI_PROFILE_AXIWRCNTRVAL_2).............................................................................................. 326858.5.24 HPSMI AXI Master 3 Read Port Profile Counter Value Register(HPSMI_PROFILE_AXIRDCNTRVAL_3)............................................................................................... 326958.5.25 HPSMI AXI Master 3 Write Port Profile Counter Value Register(HPSMI_PROFILE_AXIWRCNTRVAL_3).............................................................................................. 326958.5.26 HPSMI AXI Master 4 Read Port Profile Counter Value Register(HPSMI_PROFILE_AXIRDCNTRVAL_4)............................................................................................... 327058.5.27 HPSMI AXI Master 4 Write Port Profile Counter Value Register(HPSMI_PROFILE_AXIWRCNTRVAL_4).............................................................................................. 327058.5.28 HPSMI AXI Master 5 Read Port Profile Counter Value Register(HPSMI_PROFILE_AXIRDCNTRVAL_5)............................................................................................... 3271S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 83Section number Title Page58.5.29 HPSMI AXI Master 5 Write Port Profile Counter Value Register(HPSMI_PROFILE_AXIWRCNTRVAL_5).............................................................................................. 327158.5.30 HPSMI AXI Master 6 Read Port Profile Counter Value Register(HPSMI_PROFILE_AXIRDCNTRVAL_6)............................................................................................... 327258.5.31 HPSMI AXI Master 6 Write Port Profile Counter Value Register(HPSMI_PROFILE_AXIWRCNTRVAL_6).............................................................................................. 327258.5.32 HPSMI LSB2AXI Master 0 Read Port Profile Counter Value Register(HPSMI_PROFILE_LSB2AXIRDCNTRVAL_0)......................................................................................327358.5.33 HPSMI LSB2AXI Master 0 Write Port Profile Counter Value Register(HPSMI_PROFILE_LSB2AXIWRCNTRVAL_0).....................................................................................327358.5.34 HPSMI LSB2AXI Master 1 Read Port Profile Counter Value Register(HPSMI_PROFILE_LSB2AXIRDCNTRVAL_1)......................................................................................327458.5.35 HPSMI LSB2AXI Master 1 Write Port Profile Counter Value Register(HPSMI_PROFILE_LSB2AXIWRCNTRVAL_1).....................................................................................327458.5.36 HPSMI AXI Master 0 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_0).......327558.5.37 HPSMI AXI Master 1 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_1).......327558.5.38 HPSMI AXI Master 2 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_2).......327658.5.39 HPSMI AXI Master 3 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_3).......327658.5.40 HPSMI AXI Master 4 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_4).......327758.5.41 HPSMI AXI Master 5 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_5).......327758.5.42 HPSMI AXI Master 6 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_6).......327858.5.43 HPSMI Stream DMA Read Pipeline Level 31_0 Register (HPSMI_RD_PL_LVL_31_0)........................ 327858.5.44 HPSMI Stream DMA Read Pipeline Level 63_32 Register (HPSMI_RD_PL_LVL_63_32).................... 327958.5.45 HPSMI Stream DMA Write Pipeline Level 31_0 Register (HPSMI_WR_PL_LVL_31_0)...................... 327958.5.46 HPSMI Stream DMA Write Pipeline Level 63_32 Register (HPSMI_WR_PL_LVL_63_32).................. 328058.5.47 HPSMI Stream DMA Read Address Error 0 Register (HPSMI_DSRD_ADDRESS_ERROR0)...............328058.5.48 HPSMI Stream DMA Read Address Error 1 Register (HPSMI_DSRD_ADDRESS_ERROR1)...............328158.5.49 HPSMI Stream DMA Write Address Error 0 Register (HPSMI_DSWR_ADDRESS_ERROR0).............328158.5.50 HPSMI Stream DMA Write Address Error 1 Register (HPSMI_DSWR_ADDRESS_ERROR1).............328258.5.51 HPSMI Addressing Error Address Register (HPSMI_ADDR_ERROR_ADDRVAL).............................. 328258.5.52 HPSMI Addressing Error Information Register (HPSMI_ADDR_ERROR_INFO).................................. 3283S32V234 Reference Manual, Rev. 5, 11/201984 NXP SemiconductorsSection number Title Page58.5.53 HPSMI Stream DMA Write MPU Error 0 Register (HPSMI_WRMPU_ERROR0)..................................328458.5.54 HPSMI Stream DMA Write MPU Error 1 Register (HPSMI_WRMPU_ERROR1)..................................328558.5.55 HPSMI MPU Error Address Register (HPSMI_WRMPU_ERROR_ADDR)............................................ 328558.5.56 HPSMI MPU Error Information Register (HPSMI_WRMPU_ERROR_INFO)........................................ 328658.5.57 HPSMI_PM_ERROR_1_2.......................................................................................................................... 328758.5.58 HPSMI_PM_ERROR_ADDR_1_2............................................................................................................. 328758.5.59 HPSMI_PM_ERROR_INFO_1_2............................................................................................................... 328858.5.60 HPSMI Error Inject Register (HPSMI_ECC_ERR_INJECT).....................................................................328958.5.61 HPSMI ECC Error Counter Reset Mask (HPSMI_ECC_ERRCNTR_MASK)..........................................329058.5.62 Single Error counter for SEG1_2 Register (HPSMI_ECC_SINGLE_ERRCNTR_1_2)............................ 329258.5.63 Uncorrectable Error Counter for Seg1_2 Register (HPSMI_ECC_UNCORR_ERRCNTR_1_2)..............329458.5.64 HPSMI ECC Error Address Segment 1 Register (HPSMI_ECC_ERRADDR_SEG1).............................. 329558.5.65 HPSMI ECC Error Data 31:0 for Segment 1 Register (HPSMI_ECC_ERRDATA0_SEG1).................... 329658.5.66 HPSMI ECC Error Data 63:32 for Segment 1 Register (HPSMI_ECC_ERRDATA1_SEG1).................. 329658.5.67 HPSMI ECC Error Information Segment 1 Register (HPSMI_ECC_ERRINFO_SEG1).......................... 329758.5.68 HPSMI ECC Error Address Segment 2 Register (HPSMI_ECC_ERRADDR_SEG2).............................. 329858.5.69 HPSMI ECC Error Data 31:0 for Segment 2 Register (HPSMI_ECC_ERRDATA0_SEG2).................... 329858.5.70 HPSMI ECC Error Data 63:32 for Segment 2 Register (HPSMI_ECC_ERRDATA1_SEG2).................. 329958.5.71 HPSMI ECC Error Information Segment 2 Register (HPSMI_ECC_ERRINFO_SEG2).......................... 330058.5.72 HPSMI_ECC_ERROCCURRED_SEG1_2.................................................................................................330158.5.73 HPSMI ECC Error Address for Even Banks of Segment0 Register(HPSMI_ECC_ERRADDR_SEG0_EVEN)................................................................................................330258.5.74 HPSMI ECC Error Address for Odd Banks of Segment0 Register(HPSMI_ECC_ERRADDR_SEG0_ODD)..................................................................................................330258.5.75 HPSMI ECC Error Data 31:0 for even banks of Segment0 Register(HPSMI_ECC_ERRDATA0_SEG0_EVEN)..............................................................................................330358.5.76 HPSMI ECC Error Data 63:32 for even banks of Segment0 Register(HPSMI_ECC_ERRDATA1_SEG0_EVEN)..............................................................................................330358.5.77 HPSMI ECC Error Data 31:0 for odd banks of Segment0 Register(HPSMI_ECC_ERRDATA0_SEG0_ODD)................................................................................................3304S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 85Section number Title Page58.5.78 HPSMI ECC Error Data 63:32 for odd banks of Segment0 Register(HPSMI_ECC_ERRDATA1_SEG0_ODD)................................................................................................330458.5.79 HPSMI ECC Error Information Segment 0 Register (HPSMI_ECC_ERRINFO_SEG0).......................... 330558.5.80 HPSMI_ECC_ERROCCURED_SEG0....................................................................................................... 330758.5.81 ECC Single Error Counter for Odd and Even Bank Register(HPSMI_ECC_SINGLE_ERRCNTR_ODD_EVEN_0)............................................................................. 330858.5.82 ECC Uncorectable Error Conter for Odd and Even Bank Register(HPSMI_ECC_UNCORR_ERRCNTR_ODD_EVEN_0)...........................................................................331158.5.83 HPSMI_PM_ERROR_0.............................................................................................................................. 331358.5.84 HPSMI_PM_ERROR_ADDR_0................................................................................................................. 331358.5.85 HPSMI_PM_ERROR_INFO_0................................................................................................................... 331458.5.86 HPSMI_POWMOD_CTRL_0..................................................................................................................... 331558.5.87 HPSMI_POWMOD_CTRL_0_8_11........................................................................................................... 331658.5.88 HPSMI_POWMOD_CTRL_1_2................................................................................................................. 331658.5.89 HPSMI_QOS_PRIORITY........................................................................................................................... 331758.5.90 Interconnect Parity Checking Global Enable Register (HPSMI_IPCGE)................................................... 331858.5.91 Interconnect Parity Read Checking Enable Register (HPSMI_IPRCE)......................................................331958.5.92 HPSMI_IPWCE........................................................................................................................................... 332158.5.93 Interconnect Parity Write Address Checking Enable Register (HPSMI_IPWACE)...................................332358.5.94 Interconnect Parity Read Address Checking Enable Register (HPSMI_IPRACE).....................................332558.5.95 Interconnect Parity Checking Global Injection Enable Register (HPSMI_IPCGIE).................................. 332758.6 Functional Description..................................................................................................................................................332758.7 Feature Description:......................................................................................................................................................333158.7.1 Stream DMA Master Priority.......................................................................................................................333158.7.2 NIC301 functional details for HPSMI MSB................................................................................................333258.7.3 NIC Integrity Check(parity).........................................................................................................................333858.7.4 Error Correcting Code(ECC)....................................................................................................................... 334158.7.5 Power Modes................................................................................................................................................334758.7.6 Memory Protection Unit.............................................................................................................................. 334758.7.7 Error injection.............................................................................................................................................. 3348S32V234 Reference Manual, Rev. 5, 11/201986 NXP SemiconductorsSection number Title Page58.8 Debug Features............................................................................................................................................................. 335058.8.1 Profiling:...................................................................................................................................................... 335058.8.2 Debug Watchpoints......................................................................................................................................335158.9 Interrupts, Error Reporting and Error Response...........................................................................................................336858.10 Implementation Procedure............................................................................................................................................337258.11 HTM Implementation Procedure.................................................................................................................................. 3373Chapter 59MIPICSI259.1 Chip-specific MIPICSI2 Information........................................................................................................................... 337559.2 About this module.........................................................................................................................................................337559.2.1 Definition..................................................................................................................................................... 337559.2.2 MIPICSI2 Copyright....................................................................................................................................337659.2.3 Features........................................................................................................................................................ 337659.2.4 MIPICSI2 compliance..................................................................................................................................337759.2.5 Modes of operation...................................................................................................................................... 337759.2.6 Clocking....................................................................................................................................................... 337759.3 MIPICSI2......................................................................................................................................................................337759.3.1 MIPICSI2 block diagram............................................................................................................................. 337759.3.2 MIPICSI2 components.................................................................................................................................337859.3.3 MIPICSI2 signals.........................................................................................................................................337859.4 DPHY RX..................................................................................................................................................................... 337959.4.1 DPHY RX block diagram............................................................................................................................ 337959.4.2 DPHY RX components................................................................................................................................338059.4.3 DPHY RX signals........................................................................................................................................ 338059.4.4 Calibrator..................................................................................................................................................... 338159.4.5 Receiver....................................................................................................................................................... 338159.5 RX controller core.........................................................................................................................................................338259.5.1 RX controller core block diagram................................................................................................................338259.5.2 RX controller core components................................................................................................................... 3383S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 87Section number Title Page59.5.3 RX controller core signals............................................................................................................................338459.6 HPSMI gasket............................................................................................................................................................... 338459.6.1 MIPICSI2 subsystem output data format.....................................................................................................338459.7 Using MIPICSI2........................................................................................................................................................... 338559.7.1 Initializing the MIPICSI2 subsystem...........................................................................................................338559.7.2 Calculate the required settle time for DPHY RX.........................................................................................338559.7.3 Override auto calibration values.................................................................................................................. 338659.7.4 Place receiver in high-speed mode...............................................................................................................338659.7.5 Place receiver in ultra low-power mode...................................................................................................... 338759.7.6 Video Data Capture......................................................................................................................................338759.7.7 Embedded Data Capture.............................................................................................................................. 338959.7.8 Understanding MIPICSI2 compliant error levels........................................................................................ 339259.7.9 Decipher error sources and interrupt signals................................................................................................339359.7.10 Interrupts...................................................................................................................................................... 339459.8 Memory map and register definition.............................................................................................................................339559.8.1 RX Controller Configuration Register (MIPICSI2_CONC)....................................................................... 339959.8.2 PHY Configuration Register (MIPICSI2_PHYC).......................................................................................340059.8.3 Clock Configuration Status Register (MIPICSI2_CLKCS)........................................................................ 340159.8.4 D-PHY Lane 0 Configuration Status Register (MIPICSI2_LAN0CS)....................................................... 340359.8.5 D-PHY Data LANE 1 Configuration Status Register (MIPICSI2_LAN1CS)............................................ 340559.8.6 LANE 2 Configuration/Status Register (MIPICSI2_LAN2CS)..................................................................340759.8.7 LANE3 Configuration Status Register (MIPICSI2_LAN3CS)................................................................... 340959.8.8 External Resistor Configuration Status Register (MIPICSI2_RESCS).......................................................341159.8.9 Status Register (MIPICSI2_SR).................................................................................................................. 341259.8.10 DATAID VC Report Register (MIPICSI2_DATAVCR)............................................................................341359.8.11 Protocol and Packet Error Register (MIPICSI2_ERRPPREG)................................................................... 341459.8.12 Error Position (MIPICSI2_ERRPOS)..........................................................................................................341559.8.13 Protocol Packet Error Interrupt Enable (MIPICSI2_ERPPINTEN)............................................................ 341659.8.14 PHY Error Report Register (MIPICSI2_ERRPHY)....................................................................................3417S32V234 Reference Manual, Rev. 5, 11/201988 NXP SemiconductorsSection number Title Page59.8.15 Phy Error Interrupt Enable Register (MIPICSI2_ERPHYIE)..................................................................... 342059.8.16 RX Enable Register (MIPICSI2_RXEN).................................................................................................... 342259.8.17 Alpha Value Register (MIPICSI2_ALPHAVAL)....................................................................................... 342359.8.18 Start Pointer for Virtual Channel data in SRAM (MIPICSI2_SRTPTRn).................................................. 342359.8.19 Buffer Line Length for Virtual Channel Data (MIPICSI2_BUFLLENn)................................................... 342459.8.20 LINE LENGTH for Virtual Channel data (MIPICSI2_LINLENn).............................................................342559.8.21 NUMBER OF LINES ON A VC (MIPICSI2_NUMLINEn)...................................................................... 342659.8.22 Next Line In SRAM for a particular VC (MIPICSI2_NXTLINn).............................................................. 342759.8.23 Total Lines received for Virtual Channel (MIPICSI2_TOTLINn)..............................................................342759.8.24 Expected Number of Lines on a VC (MIPICSI2_EXPCTDLn)..................................................................342859.8.25 Lines Per Done Indication for a VC (MIPICSI2_LPDIn)........................................................................... 342859.8.26 Stream Data Type for VC (MIPICSI2_STRMDTn)....................................................................................342959.8.27 ERROR LENGTH (MIPICSI2_ERRLENn)............................................................................................... 343059.8.28 Error Line (MIPICSI2_ERRLINEn)............................................................................................................343059.8.29 Enable Channel (MIPICSI2_ENABLECH).................................................................................................343159.8.30 Interrupt Enable on Virtual Channel (MIPICSI2_INTRENVC)................................................................. 343259.8.31 Interrupt Status For Virtual Channel (MIPICSI2_INTRSVC).................................................................... 343459.8.32 Embedded Data Start Pointer (MIPICSI2_EMBEDSP).............................................................................. 343659.8.33 Embedded Data Length (MIPICSI2_EMBEDLEN)....................................................................................343659.8.34 Embedded Data Next Pointer (MIPICSI2_EMBEDNP)............................................................................. 343759.8.35 Embedded Data Enable (MIPICSI2_EMBEDENB)....................................................................................343859.8.36 Embedded data Received Count (MIPICSI2_EMBEDRCVD)...................................................................343959.8.37 Embedded Data Master Channel (MIPICSI2_EMBMSTR)........................................................................344059.8.38 Embedded Data Interrupt Enable (MIPICSI2_EMBEDIE).........................................................................344159.8.39 Embedded Data Interrupt Status Register (MIPICSI2_EMBEDINTS).......................................................344259.8.40 Embedded Lines for genertaion of first interrupt (MIPICSI2_EMBEDIRQ1)........................................... 344359.8.41 Embedded Lines after which second interrpt is generated (MIPICSI2_EMBEDIRQ2)............................. 344359.9 NOTICE OF DISCLAIMER........................................................................................................................................ 3444Chapter 60S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 89Section number Title PageH264 Encoder (H264_ENC)60.1 Chip-specific H264_ENC information......................................................................................................................... 344760.2 Introduction...................................................................................................................................................................344760.2.1 Features........................................................................................................................................................ 344760.2.2 Abbreviations and Acronyms.......................................................................................................................344860.2.3 Block Diagram............................................................................................................................................. 344860.2.4 Modes of Operation..................................................................................................................................... 344960.2.5 Interrupts...................................................................................................................................................... 345160.3 Memory map /Register Definition................................................................................................................................345460.3.1 Module Configuration Register (H264_ENC_MCR).................................................................................. 345660.3.2 Video Configuration Register (H264_ENC_VCR)..................................................................................... 345860.3.3 Video Input Alarm Register (H264_ENC_VI_ALARM)............................................................................345960.3.4 Fetch Macroblock Row Register (H264_ENC_FETCH_MBRW)..............................................................346060.3.5 Video Input Circular Buffer Luma Start Address Register (H264_ENC_VI_CBUF_Y_ADDR).............. 346160.3.6 Video Input Circular Buffer Cb Start Address Register (H264_ENC_VI_CBUF_CB_ADDR)................ 346160.3.7 Video Input Circular Buffer Cr Start Address Register (H264_ENC_VI_CBUF_CR_ADDR)................. 346260.3.8 Video Input Number of Lines Register (H264_ENC_VI_NRLINES)........................................................ 346360.3.9 Rate Flow Control Register (H264_ENC_RATE_FLOW_CTRL)............................................................. 346460.3.10 Output Circular Buffer Start Address Register (H264_ENC_OUT_CBUF_START_ADDR)...................346460.3.11 Output Circular Buffer End Address Register (H264_ENC_OUT_CBUF_END_ADDR)........................ 346560.3.12 Ouput Circular Buffer Alarm Address Register (H264_ENC_OUT_CBUF_ALARM_ADDR)............... 346660.3.13 Output Circular Buffer Current Address Register (H264_ENC_OUT_CBUF_CURR_ADDR)................346760.3.14 Output Circular Buffer Vend Address Register (H264_ENC_OUT_CBUF_VEND_ADDR)................... 346860.3.15 Line Counter Status Register (H264_ENC_LINE_CNTR_STAT)............................................................. 346960.3.16 Interrupt Status Register (H264_ENC_ISR)................................................................................................347060.3.17 Interrupt Enable Register (H264_ENC_IER).............................................................................................. 347260.3.18 Testline Configuration Register (H264_ENC_TESTLINE_CFG).............................................................. 347460.3.19 Testline Start Location Register (H264_ENC_TESTLINE_STRT_LOC)..................................................347560.3.20 Testline Luma Value Register (H264_ENC_TESTLINE_LUMA_VAL).................................................. 3476S32V234 Reference Manual, Rev. 5, 11/201990 NXP SemiconductorsSection number Title Page60.3.21 Testline Chroma Cb Value Register (H264_ENC_TESTLINE_CB_VAL)................................................347760.3.22 Testline Chroma Cr Value Register (H264_ENC_TESTLINE_CR_VAL)................................................ 347860.3.23 ULLVC Frame Rate Register (H264_ENC_ULLVC_FRAME_RATE).................................................... 347860.3.24 ULLVC Quantization Parameter Initial Register (H264_ENC_ULLVC_QP_INIT)..................................347960.3.25 ULLVC Quantization Parameter Range Register (H264_ENC_ULLVC_QP_RANGE)........................... 347960.3.26 ULLVC Bits Per Macroblock Row Register (H264_ENC_ULLVC_BITS_PER_MB_ROW)..................348060.3.27 ULLVC Fallback QP Limit Register (H264_ENC_ULLVC_QP_FALLBACK_LIMIT).......................... 348160.3.28 ULLVC Increment QP Register (H264_ENC_ULLVC_QP_INC).............................................................348160.3.29 ULLVC Increment Threshold Register (H264_ENC_ULLVC_QP_INC_THLDn)................................... 348360.3.30 ULLVC Decrement QP Register (H264_ENC_ULLVC_QP_DEC).......................................................... 348360.3.31 ULLVC Decrement Threshold Register (H264_ENC_ULLVC_QP_DEC_THLDn).................................348560.3.32 ULLVC Wait Frames Register (H264_ENC_ULLVC_WAIT_FRAMES)................................................ 348660.3.33 ULLVC Disable DBF Register (H264_ENC_ULLVC_DISABLE_DBF)................................................. 348660.3.34 ULLVC Bitrate Stream Register (H264_ENC_ULLVC_BITRATE_STREAM).......................................348760.4 Functional Description..................................................................................................................................................348760.4.1 Input Stream DMA.......................................................................................................................................348760.4.2 Encoder Core Functional Description..........................................................................................................349160.4.3 Output Stream DMA....................................................................................................................................349760.4.4 Data Mode Chroma......................................................................................................................................350060.4.5 Testline Feature............................................................................................................................................350160.4.6 Rate Flow Control........................................................................................................................................350260.4.7 Endianess..................................................................................................................................................... 350460.5 Encoder SW flow and handshaking with Cortex-A53 and Sequencer......................................................................... 350560.5.1 Encoder Input...............................................................................................................................................350560.5.2 Encoder Output............................................................................................................................................ 350660.5.3 Encoder Input and Output............................................................................................................................ 350760.6 Use Case........................................................................................................................................................................3507Chapter 61H264 Decoder (H264_DEC)S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 91Section number Title Page61.1 Chip-specific H264_DEC information......................................................................................................................... 350961.2 Performance Considerations......................................................................................................................................... 350961.3 Introduction...................................................................................................................................................................351061.3.1 Features........................................................................................................................................................ 351061.3.2 Abbreviations and Acronyms.......................................................................................................................351161.3.3 Block Diagram............................................................................................................................................. 351161.4 Modes of Operation...................................................................................................................................................... 351361.5 Interrupts.......................................................................................................................................................................351661.6 Memory map /Register Definition................................................................................................................................351761.6.1 MODULE CONFIGURATION REGISTER (H264_DEC_MCR)............................................................. 352461.6.2 TIMEOUT CONFIGURATION REGISTER (H264_DEC_TIMEOUT_CFG)......................................... 352861.6.3 STREAM VIDEO CONFIGURATION REGISTER (H264_DEC_STRn_VCR)......................................352961.6.4 STREAM PACKET ADDRESS REGISTER (H264_DEC_STR_PKT_ADDR).......................................353061.6.5 STREAM TRIGGER AND PACKET CONFIGURATION REGISTER(H264_DEC_STR_TRIG_PKT_CFG)........................................................................................................ 353161.6.6 STREAM PACKET FIFO WATERMARK REGISTER (H264_DEC_STR_PKT_FIFO_WMRK).........353261.6.7 STREAM 0 and 1 PACKET FIFO STATUS REGISTER (H264_DEC_STR_01_PKT_FIFO_STAT).... 353261.6.8 STREAM 2 and 3 PACKET FIFO STATUS REGISTER (H264_DEC_STR_23_PKT_FIFO_STAT).... 353561.6.9 STREAM 0 PACKET STATUS REGISTER (H264_DEC_STR_0_PKTn_STATUS)............................. 353861.6.10 STREAM 1 PACKET STATUS REGISTER (H264_DEC_STR_1_PKTn_STATUS)............................. 354061.6.11 STREAM 2 PACKET STATUS REGISTER (H264_DEC_STR_2_PKTn_STATUS)............................. 354261.6.12 STREAM 3 PACKET STATUS REGISTER (H264_DEC_STR_3_PKTn_STATUS)............................. 354461.6.13 VIDEO OUTPUT STREAM LUMA ADDRESS REGISTER (H264_DEC_VO_STRn_Y_ADDR)....... 354561.6.14 VIDEO OUTPUT STREAM Cb ADDRESS REGISTER (H264_DEC_VO_STRn_CB_ADDR)............354661.6.15 VIDEO OUTPUT STREAM Cr ADDRESS REGISTER (H264_DEC_VO_STRn_CR_ADDR).............354661.6.16 VIDEO OUTPUT STREAM NUMBER OF LINES REGISTER (H264_DEC_VO_STRn_NRLINES).. 354761.6.17 RATE FLOW CONTROL REGISTER (H264_DEC_RATE_FLOW_CNTRL)....................................... 354861.6.18 LINE COUNT STATUS REGISTER (H264_DEC_LINE_CNT_STAT)..................................................354961.6.19 STATUS REGISTER (H264_DEC_STAT)................................................................................................3550S32V234 Reference Manual, Rev. 5, 11/201992 NXP SemiconductorsSection number Title Page61.6.20 INTERRUPT STATUS REGISTER (H264_DEC_ISR).............................................................................355261.6.21 INTERRUPT ENABLE REGISTER (H264_DEC_IER)............................................................................355661.6.22 TESTLINE CONFIGURATION REGISTER (H264_DEC_TESTLINE_CFG)........................................ 355861.6.23 TESTLINE PIXEL LOCATION REGISTER (H264_DEC_TESTLINE_PXL_LOC).............................. 355961.6.24 TESTLINE STREAM LUMA PIXEL VALUE (H264_DEC_TESTLINE_STRn_LUMA_VAL)............356061.6.25 TESTLINE STREAM Cb PIXEL VALUE REGISTER (H264_DEC_TESTLINE_STRn_CB_VAL)..... 356161.6.26 TESTLINE STREAM Cr PIXEL VALUE REGISTER (H264_DEC_TESTLINE_STRn_CR_VAL)......356161.6.27 ELLVC CONFIGURATION REGISTER (H264_DEC_ELLVC_CFG)....................................................356261.6.28 ELLVC REFERENCE ADDRESS CHANNEL REGISTER (H264_DEC_ELLVC_REF_ADDR_CHn)356361.6.29 ELLVC DEBUG FRAME CYCLE COUNTER THRESHOLD REGISTER(H264_DEC_ELLVC_DBG_FRAME_CYC_CNT_THRn).......................................................................356461.6.30 ELLVC STATE REGISTER (H264_DEC_ELLVC_STATE)................................................................... 356561.6.31 ELLVC PIC BIT REGISTER (H264_DEC_ELLVC_PIC_BIT)................................................................356661.6.32 ELLVC PIC WIDTH IN MBS REGISTER (H264_DEC_ELLVC_PIC_WIDTH_IN_MBS)...................356861.6.33 ELLVC PIC HEIGHT IN MBS REGISTER (H264_DEC_ELLVC_PIC_HEIGHT_IN_MBS)................356861.6.34 ELLVC PIC CROP LEFT CHANNEL 0, 1 REGISTER(H264_DEC_ELLVC_PIC_CROP_LEFT_CH_01)................................................................................... 356961.6.35 ELLVC PIC CROP LEFT CHANNEL 2, 3 REGISTER(H264_DEC_ELLVC_PIC_CROP_LEFT_CH_23)................................................................................... 357061.6.36 ELLVC PIC CROP RIGHT CHANNEL 0, 1 REGISTER(H264_DEC_ELLVC_PIC_CROP_RGHT_CH_01).................................................................................. 357061.6.37 ELLVC PIC CROP RIGHT CHANNEL 2, 3 REGISTER(H264_DEC_ELLVC_PIC_CROP_RGHT_CH_23).................................................................................. 357161.6.38 ELLVC PIC CROP TOP CHANNEL 0, 1 REGISTER(H264_DEC_ELLVC_PIC_CROP_TOP_CH_01)..................................................................................... 357261.6.39 ELLVC PIC CROP TOP CHANNEL 2, 3 REGISTER(H264_DEC_ELLVC_PIC_CROP_TOP_CH_23)..................................................................................... 357261.6.40 ELLVC PIC CROP BOTTOM CHANNEL 0, 1 REGISTER(H264_DEC_ELLVC_PIC_CROP_BTTM_CH_01)..................................................................................357361.6.41 ELLVC PIC CROP BOTTOM CHANNEL 2, 3 REGISTER(H264_DEC_ELLVC_PIC_CROP_BTTM_CH_23)..................................................................................3574S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 93Section number Title Page61.6.42 ELLVC PIC PARAM VALID REGISTER (H264_DEC_ELLVC_PIC_PARAM_VLD).........................357561.6.43 ELLVC PICTURE ORDER COUNT VALUE REGISTER (H264_DEC_ELLVC_POC_VALUE)........ 357661.6.44 ELLVC STATUS REGISTER (H264_DEC_ELLVC_STAT)................................................................... 357761.7 Functional Description..................................................................................................................................................357861.7.1 Input Stream DMA.......................................................................................................................................357861.7.2 Decoder Core............................................................................................................................................... 357961.7.3 Output Stream DMA....................................................................................................................................358161.8 Data Mode Chroma.......................................................................................................................................................358561.9 Testline..........................................................................................................................................................................358561.10 Rate Flow Control.........................................................................................................................................................358661.11 Endianess...................................................................................................................................................................... 358861.11.1 Read from SRAM........................................................................................................................................ 358861.11.2 Write to SRAM............................................................................................................................................ 358961.12 Decoder Modes............................................................................................................................................................. 358961.12.1 Constrained Baseline, Single Channel mode............................................................................................... 359061.12.2 Intra Only, Multiple channels...................................................................................................................... 359061.12.3 Constrained Baseline, Multiple channels mode...........................................................................................359161.13 Decoder SW flow and handshaking with host and Sequencer..................................................................................... 359361.14 Decoder Core Software Consideration......................................................................................................................... 359461.14.1 Reference Address for Channel's................................................................................................................. 359461.14.2 Picture Crop Status for Channel’s................................................................................................................359661.14.3 Frame Cycle Count Threshold .................................................................................................................... 3596Chapter 62JPEG Decoder (JPEG)62.1 Soft reset sequence........................................................................................................................................................359962.2 Introduction...................................................................................................................................................................359962.3 Features.........................................................................................................................................................................359962.4 Abbreviations and Acronyms....................................................................................................................................... 360062.5 Block Diagram..............................................................................................................................................................3601S32V234 Reference Manual, Rev. 5, 11/201994 NXP SemiconductorsSection number Title Page62.6 Memory Map and Registers..........................................................................................................................................360262.6.1 Stream 1 SRAM Pointer Register (JPEG_ST1_SRAM_PTR).................................................................... 361062.6.2 Stream 1 SRAM Length Value Register (JPEG_ST1_SRAM_LEN_VAL)............................................... 361062.6.3 Stream 1 Pointer FIFO Register (JPEG_ST1_PTR_FIFOn)....................................................................... 361162.6.4 Stream 1 Length Value FIFO register (JPEG_ST1_LEN_VAL_FIFOn)....................................................361162.6.5 Stream 2 SRAM Pointer register (JPEG_ST2_SRAM_PTR)..................................................................... 361262.6.6 Stream 2 SRAM Length Value Register (JPEG_ST2_SRAM_LEN_VAL)............................................... 361262.6.7 Stream 2 Pointer FIFO Register (JPEG_ST2_PTR_FIFOn)....................................................................... 361362.6.8 Stream 2 Length Value FIFO Register (JPEG_ST2_LEN_VAL_FIFOn).................................................. 361362.6.9 Stream 3 SRAM Pointer Register (JPEG_ST3_SRAM_PTR).................................................................... 361462.6.10 Stream 3 SRAM Length Value Register (JPEG_ST3_SRAM_LEN_VAL)............................................... 361462.6.11 Stream 3 Pointer FIFO Register (JPEG_ST3_PTR_FIFOn)....................................................................... 361562.6.12 Stream 3 Length Value FIFO Register (JPEG_ST3_LEN_VAL_FIFOn).................................................. 361562.6.13 Stream 4 SRAM Pointer Register (JPEG_ST4_SRAM_PTR).................................................................... 361662.6.14 Stream 4 SRAM Length Value Register (JPEG_ST4_SRAM_LEN_VAL)............................................... 361662.6.15 Stream 4 Pointer FIFO Register (JPEG_ST4_PTR_FIFOn)....................................................................... 361762.6.16 Stream 4 Length Value FIFO Register (JPEG_ST4_LEN_VAL_FIFOn).................................................. 361762.6.17 Buffer Component 1 Address Register (JPEG_BUF_C1_ADDR)..............................................................361862.6.18 Buffer Component 2 Address Register (JPEG_BUF_C2_ADDR)..............................................................361862.6.19 Buffer Component 3 Address Register (JPEG_BUF_C3_ADDR)..............................................................361962.6.20 Buffer Component 4 Address Register (JPEG_BUF_C4_ADDR)..............................................................361962.6.21 Block to Lines Number of Lines Register (JPEG_NRLINES_B2L)...........................................................362062.6.22 Block to Lines Number of Lines for Component 4 Register (JPEG_NRLINES_B2L_C4)........................362062.6.23 Timeout Register (JPEG_TIMEOUT)......................................................................................................... 362162.6.24 Wrapper Control Register (JPEG_W_CTRL1)........................................................................................... 362162.6.25 Wrapper Control Register 2 (JPEG_W_CTRL2)........................................................................................ 362262.6.26 Interrupt Enable (JPEG_INTR_EN)............................................................................................................ 362462.6.27 Wrapper Status Register (JPEG_W_STATUS)...........................................................................................362662.6.28 Error Status Register (JPEG_E_STATUS)..................................................................................................3628S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 95Section number Title Page62.6.29 Restart Interval (JPEG_RST_INTVL).........................................................................................................362862.6.30 Image Size of Stream 1 (JPEG_IMG_SZ_ST1).......................................................................................... 362962.6.31 Image Size of Stream 2 (JPEG_IMG_SZ_ST2).......................................................................................... 362962.6.32 Image Size of Stream 3 (JPEG_IMG_SZ_ST3).......................................................................................... 363062.6.33 Image Size of Stream 4 (JPEG_IMG_SZ_ST4).......................................................................................... 363062.6.34 Sampling Factor Stream 1 (JPEG_SMPL_FCTR_ST1)..............................................................................363062.6.35 Sampling Factor Stream 2 (JPEG_SMPL_FCTR_ST2)..............................................................................363162.6.36 Sampling Factor Stream 3 (JPEG_SMPL_FCTR_ST3)..............................................................................363262.6.37 Sampling Factor Stream 4 (JPEG_SMPL_FCTR_ST4)..............................................................................363262.6.38 Test Pixel Location (JPEG_TST_PXL_LOC).............................................................................................363362.6.39 Test Pixel Location 1 (JPEG_TST_PXL_LOC1)........................................................................................363462.6.40 Test Line Luma Pixel Value for Stream 1 (JPEG_TST_LINE_LUMA_ST1)............................................363462.6.41 Test Line Cb Pixel Value for Stream 1 (JPEG_TST_LINE_Cb_ST1)........................................................363562.6.42 Test Line Cr Pixel Value for Stream 1 (JPEG_TST_LINE_Cr_ST1)......................................................... 363662.6.43 Test Line Luma Pixel Value for Stream 2 (JPEG_TST_LINE_LUMA_ST2)............................................363662.6.44 Test Line Cb Pixel Value for Stream 2 (JPEG_TST_LINE_Cb_ST2)........................................................363762.6.45 Test Line Cr Pixel Value for Stream 2 (JPEG_TST_LINE_Cr_ST2)......................................................... 363762.6.46 Test Line Luma Pixel Value for Stream 3 (JPEG_TST_LINE_LUMA_ST3)............................................363862.6.47 Test Line Cb Pixel Value for Stream 3 (JPEG_TST_LINE_Cb_ST3)........................................................363962.6.48 Test Line Cr Pixel Value for Stream 3 (JPEG_TST_LINE_Cr_ST3)......................................................... 363962.6.49 Test Line Luma Pixel Value for Stream 4 (JPEG_TST_LINE_LUMA_ST4)............................................364062.6.50 Test Line Luma Cb Pixel Value for Stream 4 (JPEG_TST_LINE_Cb_ST4)............................................. 364062.6.51 Test Line Cr Pixel Value for Stream 4 (JPEG_TST_LINE_Cr_ST4)......................................................... 364162.6.52 Control Register (JPEG_JPEG_CTRL)....................................................................................................... 364262.6.53 Status 1 Register (JPEG_JPEG_STATUS1)................................................................................................364262.6.54 Status 2 Register (JPEG_JPEG_STATUS2)................................................................................................364362.6.55 Status 3 Register (JPEG_JPEG_STATUS3)................................................................................................364362.6.56 Status 4 Register (JPEG_JPEG_STATUS4)................................................................................................364462.6.57 Status 5 Register (JPEG_JPEG_STATUS5)................................................................................................3644S32V234 Reference Manual, Rev. 5, 11/201996 NXP SemiconductorsSection number Title Page62.6.58 Status 6 Register (JPEG_JPEG_STATUS6)................................................................................................364562.6.59 Status 7 Register (JPEG_JPEG_STATUS7)................................................................................................364562.6.60 Status 8 Register (JPEG_JPEG_STATUS8)................................................................................................364662.6.61 Status 9 Register (JPEG_JPEG_STATUS9)................................................................................................364662.6.62 Status 10 Register (JPEG_JPEG_STATUS10)............................................................................................364762.6.63 Status 11 Register (JPEG_JPEG_STATUS11)............................................................................................364762.6.64 Status 12 Register (JPEG_JPEG_STATUS12)............................................................................................364862.6.65 Status 13 Register (JPEG_JPEG_STATUS13)............................................................................................364962.7 Functional description...................................................................................................................................................365062.7.1 JPEG Decoder.............................................................................................................................................. 365062.7.2 Input Stream DMA Interface....................................................................................................................... 365062.7.3 Output Stream DMA Interface.....................................................................................................................365162.7.4 Stream Wrapper........................................................................................................................................... 365662.7.5 Testline Feature............................................................................................................................................365762.7.6 JPEG Decoder Core functionality................................................................................................................365762.7.7 Programming Constraints............................................................................................................................ 365862.8 Copyright Notice...........................................................................................................................................................3659Chapter 63FastDMA (FDMA)63.1 Chip-specific FDMA information.................................................................................................................................366163.1.1 Programming Guidelines............................................................................................................................. 366163.2 Introduction...................................................................................................................................................................366263.3 Overview.......................................................................................................................................................................366263.3.1 Block diagram.............................................................................................................................................. 366263.3.2 Features........................................................................................................................................................ 366463.3.3 Acronyms and abbreviations........................................................................................................................366463.3.4 Modes of operation...................................................................................................................................... 366463.4 FastDMA Register Map ...............................................................................................................................................366563.4.1 Transfer Records List Pointer register (FDMA_XFR_REC_LIST_PTR)...................................................3666S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 97Section number Title Page63.4.2 Total entries in Transfer Record List (FDMA_XFR_REC_CNT).............................................................. 366663.4.3 Transfer Record number for current Line transfer (FDMA_XFR_REC_NUM).........................................366763.4.4 DDR and SRAM Line numbers for current transfer (FDMA_XFR_LINE_NUM).................................... 366763.4.5 Line increment value for SRAM and DDR (FDMA_LINE_INCR)............................................................366863.4.6 Interrupt enable register (FDMA_IRQ_EN)................................................................................................366963.4.7 Status register (FDMA_XFR_STAT)..........................................................................................................367063.4.8 Calculated CRC value (FDMA_CALC_CRC_VAL)..................................................................................367363.4.9 Current DDR address (FDMA_CURR_DDR_PTR)................................................................................... 367363.4.10 Current SRAM address (FDMA_CURR_SRAM_PTR)............................................................................. 367463.4.11 Last completed Transfer Record Number (FDMA_XFR_REC_NUM_DONE).........................................367463.4.12 Transfer Record Number of an Erroneous Transfer (FDMA_ERR_XFR_REC_NUM).............................367563.4.13 SRAM and DDR next Line number (FDMA_NEXT_LINE)......................................................................367563.4.14 Control register (FDMA_CTRL)................................................................................................................. 367663.5 Functional Description..................................................................................................................................................367763.5.1 Basic Data Flow........................................................................................................................................... 367763.5.2 Transfer Record List.................................................................................................................................... 367763.5.3 Functional Blocks........................................................................................................................................ 368063.6 Clock and Reset............................................................................................................................................................ 3684Chapter 64Vision Sequencer (VSEQ)64.1 Chip-specific VSEQ information..................................................................................................................................368564.2 VSEQ KRAM and ISP Debug registers....................................................................................................................... 368664.3 Introduction...................................................................................................................................................................368664.4 Features.........................................................................................................................................................................368664.5 Acronyms and abbreviations.........................................................................................................................................368764.6 Block diagram...............................................................................................................................................................368864.7 Design Overview.......................................................................................................................................................... 368964.7.1 Initialization Sequence and Functional Modes............................................................................................ 369064.7.2 System Memory Map...................................................................................................................................3691S32V234 Reference Manual, Rev. 5, 11/201998 NXP SemiconductorsSection number Title Page64.7.3 Interrupt Vector Assignment........................................................................................................................369364.7.4 AIPS Peripheral Slot Assignment................................................................................................................ 369564.8 Sub-module Description............................................................................................................................................... 369864.8.1 ARM Cortex-M0 Core...............................................................................................................................369864.8.2 Crossbar-Lite (AXBS-Lite)..........................................................................................................................369964.8.3 Control Block (CTRL_BLK)....................................................................................................................... 369964.8.4 Event Controller Block (EVT_CTRL).........................................................................................................371564.8.5 Internal DMA...............................................................................................................................................374364.8.6 Address Translation for External AHB Master Port....................................................................................374864.9 Interrupts.......................................................................................................................................................................374964.10 Power Modes................................................................................................................................................................ 3750Chapter 65Video-In-Lite (VIULite)65.1 Chip-specific VIULite Information.............................................................................................................................. 375165.2 Introduction...................................................................................................................................................................375165.3 Features.........................................................................................................................................................................375265.4 Video Input Signal Mapping.........................................................................................................................................375265.5 Video Output Format.................................................................................................................................................... 375365.6 Memory map and register definition.............................................................................................................................375365.6.1 Status And Control Register (VIULite_SCR)..............................................................................................375565.6.2 Interrupt Register (VIULite_INTR).............................................................................................................375765.6.3 Detected Input Video Pixel and Line Count (VIULite_DINVSZ).............................................................. 375965.6.4 Detected Input Video Frame Length (VIULite_DINVFL)..........................................................................376065.6.5 DMA Size Register (VIULite_DMA_SIZE)............................................................................................... 376065.6.6 Base Address Of Every Field/Frame Of Picture In Memory (VIULite_DMA_ADDR).............................376165.6.7 Horizontal DMA Increment (VIULite_DMA_INC)....................................................................................376165.6.8 Input Video Pixel and Line Count (VIULite_INVSZ)................................................................................ 376265.6.9 Programable Alpha Value (VIULite_ALPHA)........................................................................................... 376265.6.10 Active Image Original Coordinate (VIULite_ACT_ORG)......................................................................... 3763S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 99Section number Title Page65.6.11 Active Image Size (VIULite_ACT_SIZE).................................................................................................. 376365.7 Functional Description..................................................................................................................................................376365.7.1 Input Formats............................................................................................................................................... 376465.7.2 Input Synchronizer.......................................................................................................................................376565.7.3 Decoder........................................................................................................................................................ 376665.7.4 DMA and De-interlace.................................................................................................................................376665.7.5 Input Video Checking.................................................................................................................................. 376765.7.6 Error Case.................................................................................................................................................... 376865.8 Initialization/Application Information..........................................................................................................................376965.8.1 Image Mode Initialization Information........................................................................................................376965.8.2 Register Configuration Timing Window..................................................................................................... 3770Chapter 66Image Signal Processor (ISP)66.1 Chip-specific ISP information...................................................................................................................................... 377166.2 Introduction...................................................................................................................................................................377266.3 Block Diagram..............................................................................................................................................................377266.4 Features.........................................................................................................................................................................377466.5 Working Principle.........................................................................................................................................................377566.6 Scalar Image Processing Unit (IPUS)...........................................................................................................................377666.6.1 IPUS Core Description ................................................................................................................................377866.6.2 Hazards and Dependencies ......................................................................................................................... 378166.6.3 Pipeline Stalls ..............................................................................................................................................378466.6.4 Core Register Memory Map ....................................................................................................................... 379466.6.5 Host Memory Map and Register Description ............................................................................................. 383766.6.6 Pipeline Description and Execution ............................................................................................................395066.6.7 Instruction Set ............................................................................................................................................. 396566.6.8 Stream DMA Interface ................................................................................................................................403566.6.9 Stream-out DMA interface ..........................................................................................................................404066.6.10 Stream DMA Interface: Orthogonality ....................................................................................................... 4042S32V234 Reference Manual, Rev. 5, 11/2019100 NXP SemiconductorsSection number Title Page66.6.11 Reverse/inverse Scan .................................................................................................................................. 404466.6.12 Unaligned Scan Line ...................................................................................................................................404666.7 Vector Image Processing Unit (IPUV)......................................................................................................................... 404766.7.1 IPUV Core description ................................................................................................................................404966.7.2 Hazards and Dependencies ......................................................................................................................... 405166.7.3 Pipeline Stalls...............................................................................................................................................405366.7.4 Core Register Memory Map ....................................................................................................................... 406366.7.5 Vector Registers...........................................................................................................................................408066.7.6 Host Memory Map and Register Description.............................................................................................. 408866.7.7 Pipeline Description and Execution ............................................................................................................416466.7.8 Instruction Set ............................................................................................................................................. 417266.7.9 Stream DMA Interface ................................................................................................................................426966.7.10 Stream-out DMA interface ..........................................................................................................................427566.7.11 Stream DMA Interface: Orthogonality ....................................................................................................... 427966.7.12 Reverse/Inverse Scan .................................................................................................................................. 428066.7.13 Unaligned Scan Line ...................................................................................................................................428266.7.14 Debug Mode cross-triggering Unit ............................................................................................................. 428366.7.15 Software Resetting and Initialization ..........................................................................................................4286Chapter 67Power Management67.1 Overview.......................................................................................................................................................................428767.2 Power Management Controller (PMC).........................................................................................................................428767.3 Supply Concept.............................................................................................................................................................428867.4 Power Modes................................................................................................................................................................ 428967.5 External Supply.............................................................................................................................................................429067.6 Voltage Monitoring.......................................................................................................................................................429067.7 Core Supply Monitor.................................................................................................................................................... 429067.8 Non Core Supplies Monitor..........................................................................................................................................429167.9 Power-on Reset............................................................................................................................................................. 4293S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 101Section number Title Page67.10 Power-up Sequence.......................................................................................................................................................429467.11 ADC Interface...............................................................................................................................................................429567.12 Safety Measures............................................................................................................................................................4296Chapter 68Power Management Controller (PMC)68.1 PMC introduction......................................................................................................................................................... 429768.1.1 Features........................................................................................................................................................ 429868.2 Memory Map and Registers..........................................................................................................................................429868.2.1 PMC Control Register (PMC_CR).............................................................................................................. 429968.2.2 PMC Reset Event Enable (PMC_REE)....................................................................................................... 430168.2.3 PMC Fault Event Enable (PMC_FEE)........................................................................................................ 430368.2.4 PMC Interrupt Event Enable (PMC_IEE)................................................................................................... 430468.2.5 PMC Fault Injection Register (PMC_FIR).................................................................................................. 430668.2.6 PMC ADC Channel Select Register (PMC_ADC_CS)...............................................................................430768.2.7 PMC Self Test Control Register (PMC_STCR).......................................................................................... 430868.3 Functional Description..................................................................................................................................................431268.3.1 POR MC_RGM phase gates........................................................................................................................ 431268.3.2 PMC Fuse Interface..................................................................................................................................... 431268.3.3 PMC Fuse Latching Mechanism..................................................................................................................431368.3.4 FCCU interface............................................................................................................................................ 431368.3.5 LVD and HVD self test mechanism............................................................................................................ 4315Chapter 69Mode Entry Module (MC_ME)69.1 Introduction...................................................................................................................................................................431969.1.1 Overview......................................................................................................................................................431969.1.2 Features........................................................................................................................................................ 432169.1.3 Use cases...................................................................................................................................................... 432169.1.4 Modes of operation...................................................................................................................................... 432469.2 External signal description............................................................................................................................................4324S32V234 Reference Manual, Rev. 5, 11/2019102 NXP SemiconductorsSection number Title Page69.3 Memory map and register definition.............................................................................................................................432569.3.1 Global Status Register (MC_ME_GS).........................................................................................................432869.3.2 Mode Control Register (MC_ME_MCTL)..................................................................................................433169.3.3 Mode Enable Register (MC_ME_ME)........................................................................................................ 433269.3.4 Interrupt Status Register (MC_ME_IS)....................................................................................................... 433469.3.5 Interrupt Mask Register (MC_ME_IM).......................................................................................................433669.3.6 Invalid Mode Transition Status Register (MC_ME_IMTS)........................................................................ 433769.3.7 Debug Mode Transition Status Register (MC_ME_DMTS)....................................................................... 433869.3.8 RESET Mode Configuration Register (MC_ME_RESET_MC)................................................................. 434269.3.9 DRUN Mode Configuration Register (MC_ME_DRUN_MC)...................................................................434469.3.10 RUN Mode Configuration Register (MC_ME_RUNn_MC).......................................................................434769.3.11 Peripheral Status Register 1 (MC_ME_PS1)...............................................................................................434969.3.12 Peripheral Status Register 2 (MC_ME_PS2)...............................................................................................435169.3.13 Peripheral Status Register 3 (MC_ME_PS3)...............................................................................................435469.3.14 Peripheral Status Register 5 (MC_ME_PS5)...............................................................................................435569.3.15 Peripheral Status Register 6 (MC_ME_PS6)...............................................................................................435869.3.16 Peripheral Status Register 7 (MC_ME_PS7)...............................................................................................436069.3.17 Run Peripheral Configuration Register (MC_ME_RUN_PCn)...................................................................436169.3.18 DEC200 Encoder Peripheral Control Register (MC_ME_PCTL39)...........................................................436369.3.19 2D-ACE Peripheral Control Register (MC_ME_PCTL40).........................................................................436469.3.20 ENET Peripheral Control Register (MC_ME_PCTL50).............................................................................436569.3.21 DMACHMUX0 Peripheral Control Register (MC_ME_PCTL49).............................................................436669.3.22 CSI0 Peripheral Control Register (MC_ME_PCTL48)...............................................................................436769.3.23 MMDC0 Peripheral Control Register (MC_ME_PCTL54)........................................................................ 436769.3.24 FlexRay Peripheral Control Register (MC_ME_PCTL52)......................................................................... 436869.3.25 PIT0 Peripheral Control Register (MC_ME_PCTL58)............................................................................... 436969.3.26 FlexTIMER0 Peripheral Control Register (MC_ME_PCTL79)................................................................. 437069.3.27 SARADC0 Peripheral Control Register (MC_ME_PCTL77).....................................................................437169.3.28 LINFLEX0 Peripheral Control Register (MC_ME_PCTL83).................................................................... 4372S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 103Section number Title Page69.3.29 IIC0 Peripheral Control Register (MC_ME_PCTL81)................................................................................437369.3.30 SPI0 Peripheral Control Register (MC_ME_PCTL87)............................................................................... 437469.3.31 CANFD0 Peripheral Control Register (MC_ME_PCTL85)....................................................................... 437569.3.32 CRC0 Peripheral Control Register (MC_ME_PCTL91)............................................................................. 437669.3.33 SPI2 Peripheral Control Register (MC_ME_PCTL89)............................................................................... 437769.3.34 SDHC Peripheral Control Register (MC_ME_PCTL93)............................................................................ 437869.3.35 VIU0 Peripheral Control Register (MC_ME_PCTL100)............................................................................437869.3.36 HPSMI Peripheral Control Register (MC_ME_PCTL104).........................................................................437969.3.37 SIPI Peripheral Control Register (MC_ME_PCTL116)..............................................................................438069.3.38 LFAST Peripheral Control Register (MC_ME_PCTL120).........................................................................438169.3.39 MMDC1 Peripheral Control Register (MC_ME_PCTL162)...................................................................... 438269.3.40 DMACHMUX1 Peripheral Control Register (MC_ME_PCTL161)...........................................................438369.3.41 CSI1 Peripheral Control Register (MC_ME_PCTL160).............................................................................438469.3.42 QUADSPI0 Peripheral Control Register (MC_ME_PCTL166)..................................................................438569.3.43 PIT1 Peripheral Control Register (MC_ME_PCTL170)............................................................................. 438669.3.44 FlexTIMER1 Peripheral Control Register (MC_ME_PCTL182)............................................................... 438769.3.45 IIC2 Peripheral Control Register (MC_ME_PCTL186)..............................................................................438869.3.46 IIC1 Peripheral Control Register (MC_ME_PCTL184)..............................................................................438969.3.47 CANFD1 Peripheral Control Register (MC_ME_PCTL190)..................................................................... 438969.3.48 LINFLEX1 Peripheral Control Register (MC_ME_PCTL188).................................................................. 439069.3.49 SPI3 Peripheral Control Register (MC_ME_PCTL194)............................................................................. 439169.3.50 SPI1 Peripheral Control Register (MC_ME_PCTL192)............................................................................. 439269.3.51 TSENS Peripheral Control Register (MC_ME_PCTL206).........................................................................439369.3.52 CRC1 Peripheral Control Register (MC_ME_PCTL204)........................................................................... 439469.3.53 VIU1 Peripheral Control Register (MC_ME_PCTL208)............................................................................439569.3.54 JPEG Peripheral Control Register (MC_ME_PCTL212)............................................................................439669.3.55 H264_DEC Peripheral Control Register (MC_ME_PCTL216).................................................................. 439769.3.56 H264_ENC Peripheral Control Register (MC_ME_PCTL220).................................................................. 439869.3.57 MBIST Peripheral Control Register (MC_ME_PCTL236).........................................................................4399S32V234 Reference Manual, Rev. 5, 11/2019104 NXP SemiconductorsSection number Title Page69.3.58 Core Status Register (MC_ME_CS)............................................................................................................ 440069.3.59 Cortex-A53_CORE0 Control Register (MC_ME_CCTL1)........................................................................ 440169.3.60 Cortex-M4 Core Control Register (MC_ME_CCTL0)............................................................................... 440269.3.61 Cortex-A53_CORE2 Control Register (MC_ME_CCTL3)........................................................................ 440369.3.62 Cortex-A53_CORE1 Control Register (MC_ME_CCTL2)........................................................................ 440469.3.63 Cortex-A53_CORE3 Control Register (MC_ME_CCTL4)........................................................................ 440569.3.64 Cortex-M4 Core Address Register (MC_ME_CADDR0)...........................................................................440669.3.65 Cortex-A53_CORE0 Core Address Register (MC_ME_CADDR1)...........................................................440769.3.66 Cortex-A53_CORE1 Core Address Register (MC_ME_CADDR2)...........................................................440869.3.67 Cortex-A53_CORE2 Core Address Register (MC_ME_CADDR3)...........................................................440969.3.68 Cortex-A53_CORE3 Core Address Register (MC_ME_CADDR4)...........................................................441069.3.69 DRUN Secondary Clock Configuration Register (MC_ME_DRUN_SEC_CC_I).....................................441169.3.70 RUN0 Secondary Clock Configuration Register (MC_ME_RUN0_SEC_CC_I).......................................441369.3.71 RUN1 Secondary Clock Configuration Register (MC_ME_RUN1_SEC_CC_I).......................................441569.3.72 RUN2 Secondary Clock Configuration Register (MC_ME_RUN2_SEC_CC_I).......................................441769.3.73 RUN3 Secondary Clock Configuration Register (MC_ME_RUN3_SEC_CC_I).......................................442069.3.74 Secondary Clock Status Register (MC_ME_SEC_CS)............................................................................... 442269.4 Functional description...................................................................................................................................................442369.4.1 Mode transition request................................................................................................................................442369.4.2 Mode details.................................................................................................................................................442569.4.3 Mode transition process............................................................................................................................... 442769.4.4 Software considerations for preventing the blocking of mode transitions...................................................443369.4.5 Protection of mode configuration registers..................................................................................................443569.4.6 Mode transition interrupts............................................................................................................................443569.4.7 Peripheral clock gating.................................................................................................................................443769.4.8 Initialization/application information.......................................................................................................... 4438Chapter 70Functional Safety Overview70.1 Introduction...................................................................................................................................................................4443S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 105Section number Title PageChapter 71Error Injection In Memories71.1 Introduction...................................................................................................................................................................444571.2 Memory map and register definition.............................................................................................................................444571.3 Persistence of error injection........................................................................................................................................ 445271.4 Procedure for using error injection in memories.......................................................................................................... 4452Chapter 72Memory Error Management Unit (MEMU)72.1 Chip-specific MEMU information................................................................................................................................445372.1.1 MEMU error sources................................................................................................................................... 445372.1.2 Reporting table implementation...................................................................................................................445372.1.3 Concurrent overflow register (OFLW) implementation.............................................................................. 445472.1.4 MEMU Error source details.........................................................................................................................445572.1.5 IPD wrapper and overflow scenarios........................................................................................................... 445772.2 Introduction...................................................................................................................................................................445872.3 Features.........................................................................................................................................................................445972.4 Block diagram...............................................................................................................................................................446072.5 Design overview........................................................................................................................................................... 446072.6 External signal description............................................................................................................................................446472.7 Memory map and register definition.............................................................................................................................446572.7.1 Overview......................................................................................................................................................446572.7.2 Control register (MEMU_CTRL)................................................................................................................ 446672.7.3 Error flag register (MEMU_ERR_FLAG)...................................................................................................446672.7.4 Debug register (MEMU_DEBUG).............................................................................................................. 446872.7.5 Peripheral RAM correctable error reporting table status register(MEMU_PERIPH_RAM_CERR_STSn).................................................................................................... 447072.7.6 Peripheral RAM correctable error reporting table address register(MEMU_PERIPH_RAM_CERR_ADDRn)................................................................................................447072.7.7 Peripheral RAM uncorrectable error reporting table status register(MEMU_PERIPH_RAM_UNCERR_STS).................................................................................................4471S32V234 Reference Manual, Rev. 5, 11/2019106 NXP SemiconductorsSection number Title Page72.7.8 Peripheral RAM uncorrectable error reporting table address register(MEMU_PERIPH_RAM_UNCERR_ADDR)............................................................................................ 447172.7.9 Peripheral RAM concurrent overflow register (MEMU_PERIPH_RAM_OFLWn).................................. 447272.8 Functional description...................................................................................................................................................447272.8.1 Initializing MEMU.......................................................................................................................................447272.8.2 Reading the reporting table.......................................................................................................................... 447372.8.3 Handling overflows (Multiple error reporting)............................................................................................4474Chapter 73Fault Collection and Control Unit (FCCU)73.1 Chip-specific FCCU information..................................................................................................................................447773.1.1 Chip-boundary FCCU signals......................................................................................................................447773.1.2 Fault signal flow diagram............................................................................................................................ 447873.1.3 FCCU FOSU Count Value...........................................................................................................................447973.1.4 FCCU chip-specific register reset values.....................................................................................................447973.1.5 FCCU_CFG register event bit values by source (N and C).........................................................................447973.1.6 FCCU False Faults Occurring During MBIST Execution .......................................................................... 448073.1.7 Enabling NCF.............................................................................................................................................. 448173.2 Introduction...................................................................................................................................................................448173.2.1 Acronyms and abbreviations........................................................................................................................448273.3 Main features................................................................................................................................................................ 448373.4 Block diagram...............................................................................................................................................................448373.5 Signal description..........................................................................................................................................................448573.5.1 Signals..........................................................................................................................................................448573.6 Put FCCU in Configuration or Normal state................................................................................................................ 448773.6.1 Introduction..................................................................................................................................................448773.6.2 About changing states.................................................................................................................................. 448773.6.3 About locking the configuration.................................................................................................................. 448773.6.4 Put FCCU in Configuration state................................................................................................................. 448873.6.5 Put FCCU in Normal state........................................................................................................................... 4488S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 107Section number Title Page73.7 Run operations.............................................................................................................................................................. 448973.7.1 Introduction..................................................................................................................................................448973.7.2 About running operations.............................................................................................................................448973.7.3 Run an operation.......................................................................................................................................... 448973.8 Functional description...................................................................................................................................................449073.8.1 Definitions....................................................................................................................................................449073.8.2 FSM description...........................................................................................................................................449173.8.3 Fault priority scheme and nesting................................................................................................................ 449373.8.4 Fault recovery.............................................................................................................................................. 449473.8.5 NMI/WKPU interface.................................................................................................................................. 449673.8.6 STCU interface............................................................................................................................................ 449773.8.7 Nonvolatile memory interface..................................................................................................................... 449873.8.8 EOUT interface............................................................................................................................................ 449973.8.9 Fault signal flow...........................................................................................................................................450673.9 Register descriptions.....................................................................................................................................................450673.9.1 Control (FCCU_CTRL)............................................................................................................................... 450973.9.2 Control Key (FCCU_CTRLK).....................................................................................................................451173.9.3 Configuration (FCCU_CFG)....................................................................................................................... 451273.9.4 Noncritical Fault Configuration (FCCU_NCF_CFGn)............................................................................... 451573.9.5 Noncritical Fault State Configuration (FCCU_NCFS_CFGn).................................................................... 451673.9.6 Noncritical Fault Status (FCCU_NCF_Sn)..................................................................................................451773.9.7 Noncritical Fault Key (FCCU_NCFK)........................................................................................................ 451973.9.8 Noncritical Fault Enable (FCCU_NCF_En)................................................................................................ 452073.9.9 Noncritical Fault Timeout Enable (FCCU_NCF_TOEn)............................................................................ 452173.9.10 Noncritical Fault Timeout (FCCU_NCF_TO).............................................................................................452273.9.11 Configuration-State Timer Interval (FCCU_CFG_TO).............................................................................. 452273.9.12 IO Control (FCCU_EINOUT)..................................................................................................................... 452373.9.13 Status (FCCU_STAT)..................................................................................................................................452573.9.14 NA Freeze Status (FCCU_N2AF_STATUS).............................................................................................. 4527S32V234 Reference Manual, Rev. 5, 11/2019108 NXP SemiconductorsSection number Title Page73.9.15 AF Freeze Status (FCCU_A2FF_STATUS)................................................................................................452873.9.16 NF Freeze Status (FCCU_N2FF_STATUS)................................................................................................452973.9.17 FA Freeze Status (FCCU_F2A_STATUS)..................................................................................................453073.9.18 Noncritical Fault Fake (FCCU_NCFF)........................................................................................................453173.9.19 IRQ Status (FCCU_IRQ_STAT)................................................................................................................. 453273.9.20 IRQ Enable (FCCU_IRQ_EN).................................................................................................................... 453373.9.21 X Timer (FCCU_XTMR)............................................................................................................................ 453473.9.22 Mode Controller Status (FCCU_MCS)........................................................................................................453573.9.23 Transient Configuration Lock (FCCU_TRANS_LOCK)............................................................................453773.9.24 Permanent Configuration Lock (FCCU_PERMNT_LOCK).......................................................................453873.9.25 Delta T (FCCU_DELTA_T)........................................................................................................................453873.9.26 IRQ Alarm Enable (FCCU_IRQ_ALARM_ENn).......................................................................................453973.9.27 NMI Enable (FCCU_NMI_ENn).................................................................................................................454073.9.28 Noncritical Fault-State EOUT Signaling Enable (FCCU_EOUT_SIG_ENn)............................................ 454173.9.29 Configuration registers.................................................................................................................................454273.9.30 FCCU_CFG register bit value sources (N and C) by event.........................................................................454373.10 FCCU Output Supervision Unit....................................................................................................................................454473.11 Use cases and limitations..............................................................................................................................................454673.11.1 Configuration guidelines..............................................................................................................................454673.11.2 Recommendations to configure FCCU........................................................................................................ 4547Chapter 74Self-Test Control Unit (STCU2)74.1 Chip-specific Self Test Control Unit (STCU2) information.........................................................................................454974.1.1 Supported BIST sequences.......................................................................................................................... 454974.1.2 Self Test Overview.......................................................................................................................................454974.1.3 STCU2 L/MBIST mapping..........................................................................................................................455074.1.4 Wait Time for Writing to the Online Registers............................................................................................457974.1.5 On-Line Reset Generation (only MBIST)................................................................................................... 457974.1.6 On-Line Reset Generation (LBIST Enabled)...............................................................................................4579S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 109Section number Title Page74.1.7 AUTOLOCK_VALUE for Register Write Access via STCU2_SKC.........................................................458074.1.8 STCU Registers Reset Values......................................................................................................................458074.1.9 BIST interrupt support................................................................................................................................. 458074.1.10 PLL Loss of Lock During Self-test..............................................................................................................458174.2 Introduction...................................................................................................................................................................458174.3 Main features................................................................................................................................................................ 458174.4 Block diagram...............................................................................................................................................................458274.5 IPS bus interface........................................................................................................................................................... 458474.6 BISTs and BIST partitions............................................................................................................................................458574.6.1 Definition: BIST.......................................................................................................................................... 458574.6.2 Definition: BIST partition............................................................................................................................458574.6.3 Example: BIST partitions on a chip.............................................................................................................458574.6.4 Types of BIST partitions..............................................................................................................................458674.7 BIST sequences.............................................................................................................................................................458674.7.1 Definition: BIST sequence...........................................................................................................................458674.7.2 STCU2 executes MBISTs before LBISTs................................................................................................... 458674.7.3 Example: Single-phase BIST sequence....................................................................................................... 458674.7.4 Example: Multiphase BIST sequence.......................................................................................................... 458774.7.5 Types of BIST sequences.............................................................................................................................458774.7.6 Supported BIST sequences.......................................................................................................................... 458774.8 Functional description...................................................................................................................................................458774.8.1 FSM description...........................................................................................................................................458774.8.2 Reset management....................................................................................................................................... 458874.8.3 Built-in self-test scheduling......................................................................................................................... 458874.8.4 ABORT management...................................................................................................................................458974.8.5 FCCU interface............................................................................................................................................ 458974.8.6 Watchdogs....................................................................................................................................................458974.9 Register description...................................................................................................................................................... 459074.9.1 STCU2 Run Software Register (STCU2_RUNSW)....................................................................................4602S32V234 Reference Manual, Rev. 5, 11/2019110 NXP SemiconductorsSection number Title Page74.9.2 STCU2 SK Code Register (STCU2_SKC)..................................................................................................460474.9.3 STCU2 Configuration Register (STCU2_CFG).......................................................................................... 460574.9.4 STCU2 Watchdog Register Granularity (STCU2_WDG)...........................................................................460774.9.5 STCU2 Error Register (STCU2_ERR_STAT)............................................................................................ 460874.9.6 STCU2 Error FM Register (STCU2_ERR_FM)......................................................................................... 461074.9.7 STCU2 On-Line LBIST Status Register 0 (STCU2_LBSSW0)................................................................. 461174.9.8 STCU2 On-Line LBIST End Flag Register 0 (STCU2_LBESW0)............................................................ 461574.9.9 STCU2 LBIST Unrecoverable FM Register 0 (STCU2_LBUFM0)........................................................... 461874.9.10 STCU2 On-Line MBIST Status Register 0 (STCU2_MBSSW0)............................................................... 462174.9.11 STCU2 On-Line MBIST Status Register 1 (STCU2_MBSSW1)............................................................... 462574.9.12 STCU2 On-Line MBIST Status High Register 2 (STCU2_MBSSW2)...................................................... 462874.9.13 STCU2 On-Line MBIST End Flag Register 0 (STCU2_MBESW0).......................................................... 463074.9.14 STCU2 On-Line MBIST End Flag Register 1 (STCU2_MBESW1).......................................................... 463474.9.15 STCU2 On-Line MBIST End Flag Register 2 (STCU2_MBESW2).......................................................... 463874.9.16 STCU2 MBIST Unrecoverable FM Register 0 (STCU2_MBUFM0).........................................................464074.9.17 STCU2 MBIST Unrecoverable FM Register 1 (STCU2_MBUFM1).........................................................464474.9.18 STCU2 MBIST Unrecoverable FM Register 2 (STCU2_MBUFM2).........................................................464774.9.19 STCU2 LBIST Control Register (STCU2_LB_CTRLn).............................................................................464974.9.20 STCU2 LBIST PC Stop Register (STCU2_LB_PCSn)...............................................................................465274.9.21 STCU2 On-Line LBIST MISR Expected Low Register (STCU2_LB_MISRELSWn)..............................465274.9.22 STCU2 On-Line LBIST MISR Expected High Register (STCU2_LB_MISREHSWn).............................465374.9.23 STCU2 On-Line LBIST MISR Read Low Register (STCU2_LB_MISRRLSWn).................................... 465474.9.24 STCU2 On-Line LBIST MISR Read High Register (STCU2_LB_MISRRHSWn)................................... 465474.9.25 STCU2 Algorithm Select Register (STCU2_ALGOSEL)...........................................................................465574.9.26 STCU2 MBIST Stagger Register (STCU2_STGGR)..................................................................................465674.9.27 STCU2 BIST Start Register (STCU2_BSTART)........................................................................................465774.9.28 STCU2 MBIST Control Register (STCU2_MB_CTRLn).......................................................................... 465874.10 Use cases and limitations..............................................................................................................................................465974.10.1 Online self test sequence..............................................................................................................................4659S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 111Section number Title Page74.10.2 Design implementation information............................................................................................................ 4661Chapter 75Memory test and repair (MTR)75.1 Introduction...................................................................................................................................................................466375.2 Failure Diagnostic Technique.......................................................................................................................................466575.2.1 Finding Failing BIST................................................................................................................................... 466575.2.2 Finding Failing Memory with in a BIST..................................................................................................... 466675.2.3 BIST Fault Diagnostic routine..................................................................................................................... 466775.2.4 Fail Mode..................................................................................................................................................... 466875.3 MCT Memory Map and Registers................................................................................................................................ 466975.3.1 MCT Algorithm Select Register (MCT_ALGOSEL)..................................................................................466975.3.2 BIST Start register (MCT_BSTART)..........................................................................................................467175.3.3 Stagger delay register (MCT_STAG_D)..................................................................................................... 467275.4 BIST Memory Map and Registers................................................................................................................................ 467275.4.1 Memory selection register (BIST_MSRn)...................................................................................................467375.4.2 BIST start register (BIST_BSTART).......................................................................................................... 467475.4.3 BIST reset register (BIST_BRST)............................................................................................................... 467575.4.4 BIST status register (BIST_BSTAT)...........................................................................................................467675.4.5 BIST Fail Per Memory register (BIST_BFPMn).........................................................................................467775.4.6 ROM Selection register (BIST_ROM_SEL)............................................................................................... 467875.4.7 ROM General Status register (BIST_ROM_STAT)....................................................................................468075.4.8 Address Debug register (BIST_ADDR_DBG)............................................................................................468275.4.9 Data Debug register (BIST_DBGn).............................................................................................................468375.5 BCTRL Memory Map and Registers............................................................................................................................468375.5.1 BIST All register (BCTRL_BISTALL).......................................................................................................468475.5.2 BIST Select Register (BCTRL_BSEL)........................................................................................................468575.5.3 BIST Status register (BCTRL_BIST_STAT).............................................................................................. 468675.6 MTR IPS Bridge Memory Map and Registers............................................................................................................. 468775.6.1 MTR IPS Address register (MTR_IPS_ADD)............................................................................................ 4687S32V234 Reference Manual, Rev. 5, 11/2019112 NXP SemiconductorsSection number Title Page75.6.2 MTR IPS Data register (MTR_IPS_DATA)............................................................................................... 468875.6.3 MTR IPS Control register (MTR_IPS_CTRL)............................................................................................468875.6.4 Accessing MTR using IPS bridge................................................................................................................468975.7 MTR memory map........................................................................................................................................................4689Chapter 76Cyclic Redundancy Check (CRC)76.1 Chip specific CRC information.................................................................................................................................... 469376.1.1 CRC Instances..............................................................................................................................................469376.2 Introduction...................................................................................................................................................................469376.3 Main features................................................................................................................................................................ 469376.3.1 Standard features..........................................................................................................................................469476.4 Block diagram...............................................................................................................................................................469476.5 External signal description............................................................................................................................................469476.5.1 Peripheral bus interface................................................................................................................................469476.6 CRC memory map and registers...................................................................................................................................469676.6.1 Configuration Register (CRC_CFGn)......................................................................................................... 469776.6.2 Input Register (CRC_INPn).........................................................................................................................469876.6.3 Current Status Register (CRC_CSTATn).................................................................................................... 469976.6.4 Output Register (CRC_OUTPn).................................................................................................................. 469976.7 Functional description...................................................................................................................................................470076.8 Use cases.......................................................................................................................................................................470276.8.1 Programming example................................................................................................................................. 470276.8.2 Register programming..................................................................................................................................4703Chapter 77Safe State Engine (SSE)77.1 Introduction...................................................................................................................................................................470577.2 Features.........................................................................................................................................................................470577.3 Block Diagram..............................................................................................................................................................470677.4 Interrupts.......................................................................................................................................................................4707S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 113Section number Title Page77.5 Signal Description.........................................................................................................................................................470777.5.1 Signal Description........................................................................................................................................470777.6 Memory Map and Register Description........................................................................................................................470777.6.1 Configuration Register (SSE_CFG).............................................................................................................470877.6.2 Input Register (SSE_IR).............................................................................................................................. 471077.6.3 Compare Register (SSE_CR).......................................................................................................................471077.6.4 First Look Up Table Register (SSE_LUT_LSB).........................................................................................471177.6.5 Second Look Up Table Register (SSE_LUT_MSB)................................................................................... 471177.6.6 Watchdog Window Value (SSE_WD_WIN)...............................................................................................471277.6.7 Watchdog Timeout (SSE_WD_TO)............................................................................................................ 471277.6.8 Interrupt Enable Register (SSE_INT_EN)...................................................................................................471377.6.9 State Register (SSE_STATE)...................................................................................................................... 471477.7 Functional Description..................................................................................................................................................471577.7.1 Glitch Filter.................................................................................................................................................. 471577.7.2 Parity Checker..............................................................................................................................................471677.7.3 Watchdog Counter....................................................................................................................................... 4717Chapter 78Register Protection (REG_PROT)78.1 Chip specific REG_PROT information........................................................................................................................ 471978.1.1 Register Protected on Device.......................................................................................................................471978.2 Overview.......................................................................................................................................................................474178.3 Features.........................................................................................................................................................................474278.4 Modes of operation....................................................................................................................................................... 474278.5 External signal description............................................................................................................................................474378.6 Memory map and register definition.............................................................................................................................474378.6.1 Memory map................................................................................................................................................ 474478.6.2 Register descriptions.................................................................................................................................... 474678.7 Memory map and registers............................................................................................................................................474678.7.1 Soft Lock Bit Register n (REG_PROT_SLBRn).........................................................................................4747S32V234 Reference Manual, Rev. 5, 11/2019114 NXP SemiconductorsSection number Title Page78.7.2 Global Configuration Register (REG_PROT_GCR)...................................................................................474978.8 Functional description...................................................................................................................................................475078.8.1 General......................................................................................................................................................... 475078.8.2 Change lock settings.................................................................................................................................... 475078.8.3 Access errors................................................................................................................................................ 475378.9 Initialization/application information........................................................................................................................... 475478.9.1 Reset.............................................................................................................................................................475478.9.2 Writing C code using the register protection scheme.................................................................................. 4754Chapter 79Debug Architecture79.1 Introduction...................................................................................................................................................................475779.2 Features.........................................................................................................................................................................475779.3 Debug Architecture.......................................................................................................................................................476079.3.1 Debug related NCFs.....................................................................................................................................476279.3.2 Test and Debug Access Port Connectivity...................................................................................................476279.3.3 Debug Port Pin Descriptions........................................................................................................................476479.3.4 JTAG to SWD cJTAG switching sequence................................................................................................. 476479.3.5 System JTAG Controller (JTAGC)..............................................................................................................476579.3.6 Debug Access Port (DAP) TAP...................................................................................................................476679.3.7 Secure JTAG Controller (SJC).................................................................................................................... 476979.4 Trace Architecture........................................................................................................................................................ 477179.4.1 Trace Port Pin Descriptions......................................................................................................................... 477179.4.2 Trace Modules and Connectivity................................................................................................................. 477179.5 Embedded Cross Trigger.............................................................................................................................................. 477379.5.1 Cortex-M4 CTI Triggers..............................................................................................................................477479.5.2 HTM CTI Triggers.......................................................................................................................................477579.5.3 Cortex-A53 CTI Triggers.............................................................................................................................477679.5.4 Cortex-M0 DWT CTI Triggers..................................................................................................................477679.5.5 IPUS CTI Triggers....................................................................................................................................... 4777S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 115Section number Title Page79.5.6 APEX and IPUV CTI Triggers.................................................................................................................... 477779.6 Platform Debug Control Registers................................................................................................................................477879.6.1 Platform Debug Trace Control Register...................................................................................................... 477879.6.2 Platform Debug Page Control Register........................................................................................................477979.6.3 Platform Debug Miscellaneous Control Register........................................................................................ 478079.7 Debug Status and Control Registers............................................................................................................................. 478279.7.1 Miscellaneous Debug Module (MDM) AP Control Register...................................................................... 478379.7.2 Miscellaneous Debug Module (MDM) AP Status Register.........................................................................478479.7.3 Miscellaneous Debug Module (MDM) AP Status Register2.......................................................................478579.8 Debug Resets................................................................................................................................................................ 478679.9 References.....................................................................................................................................................................4786Chapter 80JTAG Controller (JTAGC)80.1 Chip specific JTAGC information................................................................................................................................478980.1.1 JTAG signal properties................................................................................................................................ 478980.2 Block diagram...............................................................................................................................................................478980.3 Features.........................................................................................................................................................................479080.4 Modes of operation....................................................................................................................................................... 479180.4.1 Reset.............................................................................................................................................................479180.4.2 IEEE 1149.1-2001 defined test modes.........................................................................................................479180.4.3 Bypass mode................................................................................................................................................ 479280.5 Introduction................................................................................................................................................................... 080.5.1 Block diagram.............................................................................................................................................. 479280.5.2 Features........................................................................................................................................................ 080.5.3 Modes of operation...................................................................................................................................... 080.6 TCK—Test clock input.................................................................................................................................................479280.7 TDI—Test data input.................................................................................................................................................... 479280.8 TDO—Test data output.................................................................................................................................................479380.9 TMS—Test mode select............................................................................................................................................... 4793S32V234 Reference Manual, Rev. 5, 11/2019116 NXP SemiconductorsSection number Title Page80.10 JCOMP—JTAG compliancy........................................................................................................................................ 479380.11 External signal description............................................................................................................................................ 080.11.1 TCK Test clock input...................................................................................................................................479480.11.2 TDI Test data input...................................................................................................................................... 080.11.3 TDO Test data output................................................................................................................................... 080.11.4 TMS Test mode select.................................................................................................................................. 080.11.5 JCOMP JTAG compliancy.......................................................................................................................... 080.12 Instruction register........................................................................................................................................................ 479480.13 Bypass register..............................................................................................................................................................479480.14 Device identification register........................................................................................................................................479580.15 Boundary scan register..................................................................................................................................................479580.16 Register description...................................................................................................................................................... 080.16.1 Instruction register....................................................................................................................................... 479680.16.2 Bypass register............................................................................................................................................. 080.16.3 Device identification register....................................................................................................................... 080.16.4 Boundary scan register................................................................................................................................. 080.17 JTAGC reset configuration...........................................................................................................................................479680.18 IEEE 1149.1-2001 (JTAG) Test Access Port............................................................................................................... 479680.19 TAP controller state machine........................................................................................................................................479780.19.1 Enabling the TAP controller........................................................................................................................ 479880.19.2 Selecting an IEEE 1149.1-2001 register...................................................................................................... 479980.20 JTAGC block instructions.............................................................................................................................................479980.20.1 IDCODE instruction.................................................................................................................................... 480080.20.2 SAMPLE/PRELOAD instruction................................................................................................................ 480080.20.3 SAMPLE instruction....................................................................................................................................480180.20.4 EXTEST External test instruction................................................................................................................480180.20.5 TEST_LEAKAGE instruction..................................................................................................................... 480180.20.6 HIGHZ instruction....................................................................................................................................... 480180.20.7 CLAMP instruction......................................................................................................................................4802S32V234 Reference Manual, Rev. 5, 11/2019NXP Semiconductors 117Section number Title Page80.20.8 BYPASS instruction.................................................................................................................................... 480280.21 Boundary scan...............................................................................................................................................................480280.22 Functional description................................................................................................................................................... 080.22.1 JTAGC reset configuration.......................................................................................................................... 480380.22.2 IEEE 11491-2001 JTAG Test Access Port.................................................................................................. 080.22.3 TAP controller state machine....................................................................................................................... 080.22.4 JTAGC block instructions............................................................................................................................ 080.22.5 Boundary scan.............................................................................................................................................. 080.23 Initialization Application information.......................................................................................................................... 0Chapter 81IEEE 1149.7 Compact JTAG Test Access Port Controller (CJTAG)81.1 References.....................................................................................................................................................................480581.2 Abbreviations................................................................................................................................................................480581.3 Introduction...................................................................................................................................................................480681.3.1 Types of operation....................................................................................................................................... 480781.3.2 Deployment by class.................................................................................................................................... 480781.3.3 1149.7 TAP signals...................................................................................................................................... 480881.3.4 TAP.7 architecture....................................................................................................................................... 480981.3.5 Protocols.......................................................................................................................................................481081.4 Operating models..........................................................................................................................................................481281.5 CJTAG implementation summary................................................................................................................................ 481281.5.1 T0 functions................................................................................................................................................. 481281.5.2 T1 functions................................................................................................................................................. 481381.5.3 T2 functions................................................................................................................................................. 481381.5.4 T3 functions................................................................................................................................................. 481381.5.5 T4 functions................................................................................................................................................. 481381.6 Ancillary services..........................................................................................................................................................481381.6.1 Overview......................................................................................................................................................481381.6.2 Resets........................................................................................................................................................... 4814S32V234 Reference Manual, Rev. 5, 11/2019118 NXP SemiconductorsSection number Title Page81.6.3 Start-up Options........................................................................................................................................... 481781.6.4 RSU operation..............................................................................................................................................481881.6.5 TAPC State Machine................................................................................................................................... 482081.7 EPU (Extended Protocol Unit) Operation.....................................................................................................................482181.7.1 EPU Operation............................................................................................................................................. 482181.7.2 EPU Registers.............................................................................................................................................. 482481.7.3 EPU Commands...........................................................................................................................................483581.7.4 EPU operating states.................................................................................................................................... 484381.7.5 System and EPU Paths.................................................................................................................................484481.8 APU (Advanced Protocol Unit) Operation...................................................................................................................484481.8.1 Overview......................................................................................................................................................484481.8.2 Operation......................................................................................................................................................484781.8.3 Escape sequences......................................................................................................................................... 484981.8.4 Signal behaviors...........................................................................................................................................484981.8.5 APU Functions.............................................................................................................................................485081.8.6 Configuration Change Packets (CP)............................................................................................................ 485681.8.7 Scan Packet.................................................................................................................................................. 485781.8.8 SP Format.....................................................................................................................................................485781.9 Functional Description..................................................................................................................................................486481.9.1 Switching from Standard Protocol to Advanced Protocol........................................................................... 4864